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參數(shù)資料
| 型號： | 9248YF-20LF |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘產(chǎn)生/分配 |
| 英文描述： | PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封裝： | 0.300 INCH, ROHS COMPLIANT, MO-118, SSOP-48 |
| 文件頁數(shù)： | 8/12頁 |
| 文件大?。?/td> | 181K |
| 代理商： | 9248YF-20LF |
5
ICS9248-20
0276E—12/15/08
PCI_STOP# Timing Diagram
PCI_STOP# is an asynchronous input to the ICS9248-20. It is used to turn off the PCICLK (0:6) clocks for low power
operation. PCI_STOP# is synchronized by the ICS9248-20 internally. The minimum that the PCICLK (0:6) clocks are
enabled (PCI_STOP# high pulse) is at least 10 PCICLK (0:6) clocks. PCICLK (0:6) clocks are stopped in a low state
and started with a full high pulse width guaranteed. PCICLK (0:6) clock on latency cycles are only one rising PCICLK.
Clock off latency is one PCICLK clock.
CPU_STOP# Timing Diagram
CPUSTOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPUCLKs for low power operation.
CPU_STOP# is synchronized by the ICS9248-20.The minimum that the CPUCLK is enabled (CPU_STOP# high pulse)
is 100 CPUCLKs. All other clocks will continue to run while the CPUCLKs are disabled. The CPUCLKs will always be
stopped in a low state and start in such a manner that guarantees the high pulse width is a full pulse. CPUCLK on latency
is less than 4 CPUCLKs and CPUCLK off latency is less than 4 CPUCLKs.
Notes:
1. All timing is referenced to the internal CPUCLK.
2. CPU_STOP# is an asynchronous input and metastable conditions may exist.
This signal is synchronized to the CPUCLKs inside the ICS9248-20.
3. All other clocks continue to run undisturbed.
4. PD# and PCI_STOP# are shown in a high (true) state.
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9148 device.)
2. PCI_STOP# is an asynchronous input, and metastable conditions may exist. This signal is required to be synchronized
inside the ICS9248-20.
3. All other clocks continue to run undisturbed.
4. PD# and CPU_STOP# are shown in a high (true) state.
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