參數(shù)資料
型號(hào): 90E32ERGI
廠(chǎng)商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類(lèi): 模擬信號(hào)調(diào)理
英文描述: SPECIALTY ANALOG CIRCUIT, PQFP48
封裝: TQFP-48
文件頁(yè)數(shù): 48/67頁(yè)
文件大小: 777K
代理商: 90E32ERGI
90E32
POLY-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC
Register
52
August 24, 2011
PoffsetA
Phase A Active Power Offset
QoffsetA
Phase A Reactive Power Offset
GainA
Phase A Active/Reactive Energy calibration gain
PhiA
Phase A calibration phase angle
The phase B and phase C’s calibration registers are similar as phase A.
4AH
PhiB
R/W
Phase B calibration phase angle
0000H
4BH
GainC
R/W
Phase C Active/Reactive Energy calibration
gain
0000H
4CH
PhiC
R/W
Phase C calibration phase angle
0000H
4DH
CS1
R/W
Checksum 1
0000H
Note: The calculation of the CS1 register is similar as the CS0 register by calculating the 41H-4CH registers. For details, please refer to IDT application note AN-644.
Address: 41H
Type: Read/Write
Default Value: 0000H
Bit
Name
Description
15-0
Offset
Power offset. Signed 16-bit integer.
Address: 42H
Type: Read/Write
Default Value: 0000H
Bit
Name
Description
15-0
Offset
Power offset. Signed 16-bit integer.
Address: 47H
Type: Read/Write
Default Value: 0000H
Bit
Name
Description
15-0
Gain
Energy calibration gain.
Signed integer.
Actual power gain = (1+ Gain)
Address: 48H
Type: Read/Write
Default Value: 0000H
Bit
Name
Description
15
DelayV
0: Delay Cycles are applied to current channel.
1: Delay Cycles are applied to voltage channel.
14:10
-
Reserved.
9:0
DelayCycles
Unit is 2.048MHz cycle. It is an unsigned 10 bit integer.
Table-6 Calibration Registers
Register
Address
Register Name
Read/Write
Type
Functional Description
Power-on Value
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