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參數(shù)資料
| 型號： | 908E425 |
| 廠商： | 飛思卡爾半導(dǎo)體(中國)有限公司 |
| 英文描述： | Integrated Quad Half H-Bridge with Power Supply, Embedded MCU, and LIN Serial Communication |
| 中文描述： | 綜合四半僅符合電源橋，嵌入式微控制器和LIN串行通信 |
| 文件頁數(shù)： | 45/49頁 |
| 文件大?。?/td> | 490K |
| 代理商： | 908E425 |
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Analog Integrated Circuit Device Data
Freescale Semiconductor
45
908E425
ADDITIONAL DOCUMENTATION
THERMAL ADDENDUM (REV 2.0)
ADDITIONAL DOCUMENTATION
THERMAL ADDENDUM (REV 2.0)
Introduction
This thermal addendum ia provided as a supplement to the 908E425 technical
data sheet. The addendum provides thermal performance information that may
be critical in the design and development of system applications. All electrical,
application and packaging information is provided in the data sheet.
Package and Thermal Considerations
This 908E425 is a dual die package. There are two heat sources in the
package independently heating with P
1
and P
2
. This results in two junction
temperatures, T
J1
and T
J2
, and a thermal resistance matrix with R
θ
JA
mn
.
For
m
,
n
= 1, R
θ
JA11
is the thermal resistance from Junction 1 to the reference
temperature while only heat source 1 is heating with P
1
.
For
m
= 1,
n
= 2, R
θ
JA12
is the thermal resistance from Junction 1 to the
reference temperature while heat source 2 is heating with P
2
. This applies to
R
θ
J21
and R
θ
J22
, respectively.
The stated values are solely for a thermal performance comparison of one
package to another in a standardized environment. This methodology is not meant to and will not predict the performance of a
package in an application-specific environment. Stated values were obtained by measurement and simulation according to the
standards listed below.
Standards
Figure 27. Thermal Land Pattern for Direct Thermal
Attachment Per JEDEC JESD51-5Thermal Test Board
54-PIN
SOICW-EP
908E425
DWB SUFFIX
98ASA10712D
54-PIN SOICW-EP
Note
For package dimensions, refer to the
908E425 device datasheet.
T
J1
T
J2
=
R
θ
JA11
R
θ
JA21
R
θ
JA12
R
θ
JA22
.
P
1
P
2
Table 14. Thermal Performance Comparison
Thermal
Resistance
1 = Power Chip, 2 = Logic Chip
[
°
C/W]
m
= 1,
n
= 1
m
= 1,
n
= 2
m
= 2,
n
= 1
m
= 2,
n
= 2
R
θ
JA
mn
(1)(2)
R
θ
JB
mn
(2)(3)
R
θ
JA
mn
(1)(4)
R
θ
JC
mn
(5)
23
20
24
9.0
6.0
10
52
47
52
1.0
0
2.0
Notes:
1.
Per JEDEC JESD51-2 at natural convection, still air
condition.
2s2p thermal test board per JEDEC JESD51-7and
JESD51-5.
Per JEDEC JESD51-8, with the board temperature on the
center trace near the power outputs.
Single layer thermal test board per JEDEC JESD51-3 and
JESD51-5.
Thermal resistance between the die junction and the
exposed pad, “infinite” heat sink attached to exposed pad.
2.
3.
4.
5.
1.0
1.0
0.2
0.2
Soldermast
openings
Thermal vias
connected to top
buried plane
54 Terminal SOIC-EP
0.65 mm Pitch
17.9 mm x 7.5 mm Body
10.3 mm x 5.1 mm Exposed Pad
* All measurements
are in millimeters
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