參數(shù)資料
型號(hào)： 89HPES8T5AZBBCI
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 總線控制器
英文描述： PCI BUS CONTROLLER, PBGA196
封裝： 15 X 15 MM, 1 MM PITCH, CABGA-196
文件頁(yè)數(shù)： 24/29頁(yè)
文件大小： 622K
代理商： 89HPES8T5AZBBCI
4 of 29
May 7, 2009
IDT 89HPES8T5A Data Sheet
General Purpose Input/Output
The PES8T5A provides 11 General Purpose Input/Output (GPIO) pins that may be used by the system designer as bit I/O ports. Each GPIO pin
may be configured independently as an input or output through software control. Some GPIO pins are shared with other on-chip functions. These
alternate functions may be enabled via software, SMBus slave interface, or serial configuration EEPROM.
Pin Description
The following tables lists the functions of the pins provided on the PES8T5A. Some of the functions listed may be multiplexed onto the same pin.
The active polarity of a signal is defined using a suffix. Signals ending with an “N” are defined as being active, or asserted, when at a logic zero (low)
level. All other signals (including clocks, buses, and select lines) will be interpreted as being active, or asserted, when at a logic one (high) level.
Signal
Type
Name/Description
PE0RP[3:0]
PE0RN[3:0]
I
PCI Express Port 0 Serial Data Receive. Differential PCI Express receive
pairs for port 0.
PE0TP[3:0]
PE0TN[3:0]
O
PCI Express Port 0 Serial Data Transmit. Differential PCI Express trans-
mit pairs for port 0.
PE2RP[0]
PE2RN[0]
I
PCI Express Port 2 Serial Data Receive. Differential PCI Express receive
pair for port 2.
PE2TP[0]
PE2TN[0]
O
PCI Express Port 2 Serial Data Transmit. Differential PCI Express trans-
mit pair for port 2.
PE3RP[0]
PE3RN[0]
I
PCI Express Port 3 Serial Data Receive. Differential PCI Express receive
pair for port 3.
PE3TP[0]
PE3TN[0]
O
PCI Express Port 3 Serial Data Transmit. Differential PCI Express trans-
mit pair for port 3.
PE4RP[0]
PE4RN[0]
I
PCI Express Port 4 Serial Data Receive. Differential PCI Express receive
pair for port 4.
PE4TP[0]
PE4TN[0]
O
PCI Express Port 4 Serial Data Transmit. Differential PCI Express trans-
mit pair for port 4.
PE5RP[0]
PE5RN[0]
I
PCI Express Port 5 Serial Data Receive. Differential PCI Express receive
pair for port 5.
PE5TP[0]
PE5TN[0]
O
PCI Express Port 5 Serial Data Transmit. Differential PCI Express trans-
mit pair for port 5.
PEREFCLKP
PEREFCLKN
I
PCI Express Reference Clock. Differential reference clock pair input. This
clock is used as the reference clock by on-chip PLLs to generate the clocks
required for the system logic and on-chip SerDes. The frequency of the dif-
ferential reference clock is determined by the REFCLKM signal.
REFCLKM
I
PCI Express Reference Clock Mode Select. This signal selects the fre-
quency of the reference clock input.
0x0 - 100 MHz
0x1 - 125 MHz
Table 2 PCI Express Interface Pins
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
89HPES8T5AZBBCI8 制造商:Integrated Device Technology Inc 功能描述:PCI Express Switch I/O Expansion Switch 8Lanes 5Ports 1-CH 196-Pin CABGA 制造商:Integrated Device Technology Inc 功能描述:PCI EXPRESS SWIT 196CABGA - Tape and Reel
89HPES8T5ZBBC 制造商:Integrated Device Technology Inc 功能描述:8-LANE 5-PORT PCI EXPRESS SWIT 324CABGA - Trays
89HPES8T5ZBBCG 制造商:Integrated Device Technology Inc 功能描述:8-LANE 5-PORT PCI EXPRESS SWIT 324CABGA - Trays
89HPES8T5ZHBC 制造商:Integrated Device Technology Inc 功能描述:PCI EXPRESS SWIT 324CABGA - Bulk
89HPES8T5ZHBCG 功能描述:接口-I/O擴(kuò)展器 RoHS:否 制造商:NXP Semiconductors 邏輯系列: 輸入/輸出端數(shù)量: 最大工作頻率:100 kHz 工作電源電壓:1.65 V to 5.5 V 工作溫度范圍:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:HVQFN-16 封裝:Reel
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