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| 型號： | 89HPES8T5AZBBCI |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI BUS CONTROLLER, PBGA196 |
| 封裝： | 15 X 15 MM, 1 MM PITCH, CABGA-196 |
| 文件頁數(shù)： | 23/29頁 |
| 文件大?。?/td> | 622K |
| 代理商： | 89HPES8T5AZBBCI |
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May 7, 2009
IDT 89HPES8T5A Data Sheet
As shown in Figure 3, the master and slave SMBuses may be used in a unified or split configuration. In the unified configuration, shown in Figure
3(a), the master and slave SMBuses are tied together and the PES8T5A acts both as a SMBus master as well as a SMBus slave on this bus. This
requires that the SMBus master or processor that has access to PES8T5A registers supports SMBus arbitration. In some systems, this SMBus master
interface may be implemented using general purpose I/O pins on a processor or micro controller, and may not support SMBus arbitration. To support
these systems, the PES8T5A may be configured to operate in a split configuration as shown in Figure 3(b).
In the split configuration, the master and slave SMBuses operate as two independent buses and thus multi-master arbitration is never required.
The PES8T5A supports reading and writing of the serial EEPROM on the master SMBus via the slave SMBus, allowing in system programming of the
serial EEPROM.
Figure 3 SMBus Interface Configuration Examples
Hot-Plug Interface
The PES8T5A supports PCI Express Hot-Plug on each downstream port. To reduce the number of pins required on the device, the PES8T5A
utilizes an external I/O expander, such as that used on PC motherboards, connected to the SMBus master interface. Following reset and configura-
tion, whenever the state of a Hot-Plug output needs to be modified, the PES8T5A generates an SMBus transaction to the I/O expander with the new
value of all of the outputs. Whenever a Hot-Plug input changes, the I/O expander generates an interrupt which is received on the IOEXPINTN input pin
(alternate function of GPIO) of the PES8T5A. In response to an I/O expander interrupt, the PES8T5A generates an SMBus transaction to read the
state of all of the Hot-Plug inputs from the I/O expander.
Bit
Slave
SMBus
Address
Master
SMBus
Address
1
SSMBADDR[1]
MSMBADDR[1]
2
SSMBADDR[2]
MSMBADDR[2]
3
SSMBADDR[3]
MSMBADDR[3]
4
0
MSMBADDR[4]
5
SSMBADDR[5]
1
61
0
71
1
Table 1 Master and Slave SMBus Address Assignment
Processor
PES8T5A
SSMBCLK
SSMBDAT
MSMBCLK
MSMBDAT
SMBus
Master
Other
SMBus
Devices
Serial
EEPROM
Processor
PES8T5A
SSMBCLK
SSMBDAT
MSMBCLK
MSMBDAT
SMBus
Master
Other
SMBus
Devices
Serial
EEPROM
...
(a) Unified Configuration and Management Bus
(b) Split Configuration and Management Buses
相關PDF資料 |
PDF描述 |
|---|---|
| 89HPES8T5AZBBC | PCI BUS CONTROLLER, PBGA196 |
| 89RW30 | SCR |
| 89RW40 | SCR |
| 8AF4NLV | 50 A, 400 V, SILICON, RECTIFIER DIODE |
| 8C443 | PIN/Preamp(Datacom, Telecom) |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| 89HPES8T5AZBBCI8 | 制造商:Integrated Device Technology Inc 功能描述:PCI Express Switch I/O Expansion Switch 8Lanes 5Ports 1-CH 196-Pin CABGA 制造商:Integrated Device Technology Inc 功能描述:PCI EXPRESS SWIT 196CABGA - Tape and Reel |
| 89HPES8T5ZBBC | 制造商:Integrated Device Technology Inc 功能描述:8-LANE 5-PORT PCI EXPRESS SWIT 324CABGA - Trays |
| 89HPES8T5ZBBCG | 制造商:Integrated Device Technology Inc 功能描述:8-LANE 5-PORT PCI EXPRESS SWIT 324CABGA - Trays |
| 89HPES8T5ZHBC | 制造商:Integrated Device Technology Inc 功能描述:PCI EXPRESS SWIT 324CABGA - Bulk |
| 89HPES8T5ZHBCG | 功能描述:接口-I/O擴展器 RoHS:否 制造商:NXP Semiconductors 邏輯系列: 輸入/輸出端數(shù)量: 最大工作頻率:100 kHz 工作電源電壓:1.65 V to 5.5 V 工作溫度范圍:- 40 C to + 85 C 安裝風格:SMD/SMT 封裝 / 箱體:HVQFN-16 封裝:Reel |
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