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參數(shù)資料
| 型號： | 853013AMLFT |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 853013 SERIES, LOW SKEW CLOCK DRIVER, 3 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20 |
| 封裝： | 7.50 X 12.80 MM, 2.30 MM HEIGHT, ROHS COMPLIANT, MS-013, MO-119, SOIC-20 |
| 文件頁數(shù)： | 11/18頁 |
| 文件大?。?/td> | 2109K |
| 代理商： | 853013AMLFT |
ICS853013
LOW SKEW, DUAL,1-TO-3, DIFFERENTIAL-TO-2.5V, 3.3V, 5V LVPECL/ECL FANOUT BUFFER
IDT / ICS 2.5V, 3.3V, 5V LVPECL/ECL FANOUT BUFFER
2
ICS853013AM REV. B OCTOBER 24, 2008
Table 1. Pin Descriptions
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Function Table
Table 3. Clock Input Function Table
NOTE 1: Please refer to the Application Information, Wiring the Differential Input to Accept Single Ended Levels.
Number
Name
Type
Description
1, 2
nQA0, QA0
Output
Differential output pair. LVPECL interface levels.
3, 8, 16
VCC
Power
Power supply pins.
4
PCLKA
Input
Pulldown
Non-inverting differential LVPECL clock input.
5
nPCLKA
Input
Pullup/
Pulldown
Inverting differential LVPECL clock input. VCC/2 default when left floating.
6
PCLKB
Input
Pulldown
Non-inverting differential LVPECL clock input.
7
nPCLKB
Input
Pullup/
Pulldown
Inverting differential LVPECL clock input. VCC/2 default when left floating.
9, 10
nQB0, QB0
Output
Differential output pair. LVPECL interface levels.
11
VEE
Power
Negative supply pin.
12, 13
nQB1, QB1
Output
Differential output pair. LVPECL interface levels.
14, 15
nQB2, QB2
Output
Differential output pair. LVPECL interface levels.
17, 18
nQA2, QA2
Output
Differential output pair. LVPECL interface levels.
19, 20
nQA1, QA1
Output
Differential output pair. LVPECL interface levels.
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
RPULLDOWN
Input Pulldown Resistor
75
k
RVCC/2
Pullup/Pulldown Resistors
50
k
Inputs
Outputs
Input to Output Mode
Polarity
PCLKA or PCLKB
nPCLKA or nPCLKB
QA0:Q2,
QB0:QB2
nQA0:nQA2,
nQB0:nQB2
0
1
LOW
HIGH
Differential to Differential
Non-Inverting
1
0
HIGH
LOW
Differential to Differential
Non-Inverting
0
Biased; NOTE 1
LOW
HIGH
Single-Ended to Differential
Non-Inverting
1
Biased; NOTE 1
HIGH
LOW
Single-Ended to Differential
Non-Inverting
Biased; NOTE 1
0
HIGH
LOW
Single-Ended to Differential
Inverting
Biased; NOTE 1
1
LOW
HIGH
Single-Ended to Differential
Inverting
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