2010-2012 Peregrine Semiconductor Corp. All rights reserved. Document No. 70-0137-0" />
參數(shù)資料
型號: 83336-22
廠商: Peregrine Semiconductor
文件頁數(shù): 5/12頁
文件大?。?/td> 0K
描述: IC PLL INTEGER-N 3GHZ 44CQFJ
標(biāo)準(zhǔn)包裝: 500
系列: UltraCMOS™
類型: 時鐘緩沖器/驅(qū)動器,多路復(fù)用器
PLL:
主要目的: 軍事應(yīng)用
輸入: 時鐘
輸出: 時鐘
電路數(shù): 1
比率 - 輸入:輸出: 1:1
差分 - 輸入:輸出: 是/無
頻率 - 最大: 3GHz
電源電壓: 2.85 V ~ 3.15 V
工作溫度: -55°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 44-CLCC 裸露焊盤
供應(yīng)商設(shè)備封裝: 44-CQFJ(16.51x16.51)
包裝: 帶卷 (TR)
其它名稱: PE83336
Product Specification
PE83336
Page 2 of 12
2010-2012 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70-0137-05 │ UltraCMOS RFIC Solutions
Table 1. Pin Descriptions
Figure 2. Pin Configuration (Top View)
44-lead CQFJ
11
12
13
14
15
16
17
10
9
8
7
6
5
4
3
2
1
44
43
42
41
40
35
34
33
32
31
30
29
36
37
38
39
18
19
20
21
22
23
24
25
26
27
28
D
0
, M
0
D
1
, M
1
D
2
, M
2
D
3
, M
3
V
DD
V
DD
S_WR, D
4
, M
4
Sdata, D
5
, M
5
Sclk, D
6
, M
6
FSELS, D
7
, Pre_en
GND
f
p
V
DD
_f
p
D
out
V
DD
C
ext
V
DD
PD_D
PD_U
V
DD
_f
c
f
c
F
in
F
in
Ho
p
_W
R
A_
W
R
M
1_W
R
V
DD
Bm
od
e
Sm
od
e,
A
3
M
2_W
R
,A
2
E_
W
R
,A
1
F
S
EL
P,
A
0
GN
D
R
3
R
2
R
1
R
0
V
DD
En
h
LD
fr
GN
D
GN
D
Figure 3. Package Photo
Pin No.
(44-lead
CQFJ)
Pin
Name
Interface
Mode
Type
Description
1
VDD
ALL
(Note 1)
Power supply input. Input may range from 2.85 V to 3.15 V. Bypassing recommended.
2
R0
Direct
Input
R Counter bit0 (LSB).
3
R1
Direct
Input
R Counter bit1.
4
R2
Direct
Input
R Counter bit2.
5
R3
Direct
Input
R Counter bit3.
6
GND
ALL
(Note 1)
Ground.
7
D0
Parallel
Input
Parallel data bus bit0 (LSB).
M0
Direct
Input
M Counter bit0 (LSB).
8
D1
Parallel
Input
Parallel data bus bit1.
M1
Direct
Input
M Counter bit1.
9
D2
Parallel
Input
Parallel data bus bit2.
M2
Direct
Input
M Counter bit2.
10
D3
Parallel
Input
Parallel data bus bit3.
M3
Direct
Input
M Counter bit3.
11
VDD
ALL
(Note 1)
Same as pin 1.
12
VDD
ALL
(Note 1)
Same as pin 1.
13
S_WR
Serial
Input
Serial load enable input. While S_WR is “l(fā)ow”, Sdata can be serially clocked. Primary register
data are transferred to the secondary register on S_WR or Hop_WR rising edge.
D4
Parallel
Input
Parallel data bus bit4
M4
Direct
Input
M Counter bit4
Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com
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