
Electrical Characteristics
16-14
Intel
82801BA ICH2 Datasheet
NOTES:
1. The V5Ref supply must power up before or simultaneous with its associated 3.3V supply, and must power
down simultaneous with or after the 3.3V supply. See
Section 2.20.4
for details.
2. The associated 3.3V and 1.8V supplies are assumed to power up or down together. The difference between
the levels of the 3.3V and 1.8V supplies must never be greater than 2.0V.
3. The VccSus supplies must
never
be active while the VccRTC supply is inactive. Likewise, the Vcc supplies
must
never
be active while the VccSus supplies are inactive.
Table 16-17. Miscellaneous Timings
Sym
Parameter
Min
Max
Units
Notes
Fig
t160
SERIRQ Setup Time to PCICLK Rising
7
ns
16-4
t161
SERIRQ Hold Time from PCICLK Rising
0
ns
16-4
t162
RI#, EXTSMI#, GPI, USB Resume Pulse Width
2
RTCCLK
16-6
t163
SPKR Valid Delay from OSC Rising
200
ns
16-3
t164
SERR# Active to NMI Active
200
ns
t165
IGNNE# Inactive from FERR# Inactive
230
ns
Table 16-18. Power Sequencing and Reset Signal Timings
Sym
Parameter
Min
Max
Units
Notes
Fig
t170
VccRTC active to RTCRST# inactive
5
-
ms
16-18
t171
V5RefSus active to VccSus3_3, VccSus1_8
active
0
-
ms
1, 2
16-18
t172
VccRTC supply active to VccSus supplies active
0
-
ms
3
16-18
t173
VccSus supplies active to RSM_PWROK active,
RSMRST# inactive
10
-
ms
16-18
,
16-20
t174
V5Ref active to Vcc3_3, Vcc1_8 active
0
-
ms
1, 2
16-18
t175
VccSus supplies active to Vcc supplies active
0
-
ms
3
16-18
t176
Vcc supplies active to PWROK, VRMPWRGD
active
10
-
ms
16-18
,
16-20
,
16-22
t177
PWROK, VRMPWRGD active to SUS_STAT#
inactive
32
34
RTCCLK
16-18
,
16-20
16-22
t178
SUS_STAT# inactive to PCIRST# inactive
1
3
RTCCLK
16-18
,
16-20
,
16-22
t179
AC_RST# active low pulse width
1
us
t180
AC_RST# inactive to BIT_CLK startup delay
162.8
ns
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