
Intel
82801BA ICH2 Datasheet
5-81
Functional Description
NOTE:
1. The OCW1 register must be read before entering Alternate Access Mode.
2. Bits 5, 3, 1, and 0 return 0.
05h
2
1
DMA Chan 2 base count
low byte
DMA Chan 2 base count
high byte
DMA Chan 3 base
address low byte
DMA Chan 3 base
address high byte
DMA Chan 3 base count
low byte
DMA Chan 3 base count
high byte
DMA Chan 0
–
3
Command
2
C4h
2
1
DMA Chan 5 base address low
byte
DMA Chan 5 base address high
byte
DMA Chan 5 base count low
byte
DMA Chan 5 base count high
byte
DMA Chan 6 base address low
byte
DMA Chan 6 base address high
byte
DMA Chan 6 base count low
byte
DMA Chan 6 base count high
byte
DMA Chan 7 base address low
byte
DMA Chan 7 base address high
byte
DMA Chan 7 base count low
byte
DMA Chan 7 base count high
byte
2
2
06h
2
1
C6h
2
1
2
2
07h
2
1
C8h
2
1
2
2
08h
6
1
CAh
2
1
2
DMA Chan 0
–
3 Request
2
3
DMA Chan 0 Mode:
Bits(1:0) = “00”
DMA Chan 1 Mode:
Bits(1:0) = “01”
DMA Chan 2 Mode:
Bits(1:0) = “10”
DMA Chan 3 Mode:
Bits(1:0) = “11”.
PIC ICW2 of Master
controller
PIC ICW3 of Master
controller
PIC ICW4 of Master
controller
PIC OCW1 of Master
controller
PIC OCW2 of Master
controller
PIC OCW3 of Master
controller
PIC ICW2 of Slave
controller
PIC ICW3 of Slave
controller
PIC ICW4 of Slave
controller
PIC OCW1 of Slave
controller
PIC OCW2 of Slave
controller
PIC OCW3 of Slave
controller
CCh
2
1
4
2
5
CEh
2
1
6
2
20h
12
1
D0h
6
1
DMA Chan 4
–
7 Command
2
2
2
DMA Chan 4
–
7 Request
3
3
DMA Chan 4 Mode:
Bits(1:0) = “00”
DMA Chan 5 Mode:
Bits(1:0) = “01”
DMA Chan 6 Mode:
Bits(1:0) = “10”
DMA Chan 7 Mode:
Bits(1:0) = “11”.
4
4
5
5
6
6
7
8
9
10
11
12
Table 5-49. Write Only Registers with Read Paths in Alternate Access Mode (Continued)
Restore Data
Restore Data
I/O
Addr
# of
Rds
Access
Data
I/O
Addr
# of
Rds
Access
Data
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