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參數(shù)資料
| 型號： | 7P512CFA4500C25 |
| 廠商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分類： | PROM |
| 英文描述： | 256M X 16 FLASH 3V PROM CARD, 250 ns, XMA50 |
| 封裝： | CARD-50 |
| 文件頁數(shù)： | 29/32頁 |
| 文件大小： | 264K |
| 代理商： | 7P512CFA4500C25 |
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White Electronic Designs Corporation Marlborough, MA (508) 485-4000
CompactFlashTM Cards
CFA45 Series
White Electronic Designs
COMPACTFLASHTM /PCMCIA-ATA MEMORY MAPPING ADDRESS
REG
A10
A[9:4]
A[3]
A[2]
A[1]
A[0]
IORD = L
IOWR = L
H
L
X
L
Read Data
Write Data
H
L
X
L
H
Error Register
Feature
H
L
X
L
H
L
Sector Count
H
L
X
L
H
Sector Number
H
L
X
L
H
L
Cylinder Low
H
L
X
L
H
L
H
Cylinder High
H
L
X
L
H
L
Drive/Head
H
L
X
L
H
Status Register
Command
H
L
X
H
L
Duplicate Read Even Data
Duplicate Write Even Data
H
L
X
H
L
H
Duplicate Read Odd Data
Duplicate Write Odd Data
H
L
X
H
L
H
Duplicate Error
Duplicate Feature
H
L
X
H
L
Alternate Status
Device Control
H
L
X
H
Drive Address
Reserved
H
X
L
Read Even Data
Write Even Data
H
X
H
Read Odd Data
Write Odd Data
THE ATA REGISTERS AND PCMCIA REGISTERS
STATUS REGISTER
DIRECTION - This register is read-only by the host.
ACCESS RESTRICTION - The contents of this register, except for BSY, will be ignored when BSY is set to one. BSY
is valid at all time. The contents of the register and all other Command Block registers are not valid while a device
is in the Sleep mode.
FUNCTIONAL DESCRIPTION - This register contains the device status. The contents of this register are updated to
reflect the current state of the device and the progress of any command being executed by the device.
BIT DESCRIPTION
7
6
5
4
3
2
1
0
BSY
DRDY
DF
DSC
DRQ
CORR
IDX
ERR
BIT 0
ERR (Error) indicates that an error occurred during execution of the previous command. The Error register has
additional information regarding the cause of the error when this bit is asserted.
BIT 1
IDX (Index) is vendor specific.
BIT 2
CORR (Corrected Data) is used to indicate a correctable data error. The definition of what constitutes a
correctable error is vendor specific.
BIT 3
DRQ (Data Request) indicates that the device is ready to transfer a word or byte between the host and the
device.
BIT 4
DSC (Device Seek Complete) indicates that the device heads are settled over a track.
BIT 5
DF (Device Fault) indicates a device fault error has been detected. The internal status or internal conditions that
causes this error to be indicated is vendor specific.
BIT 6
DRDY (Device Ready) is set to indicate that the device is capable of accepting all command codes. This bit will
be cleared at power on.
BIT 7
BSY (Busy) is set whenever the device has control of the command block registers. When the BSY bit is equal
to one, the commands written to this register will be ignored by the device.
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