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參數(shù)資料
| 型號： | 7C1359A-150 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 256K x 18 Synchronous-Pipelined Cache Tag RAM |
| 中文描述： | 256 × 18的同步高速緩存標(biāo)記內(nèi)存流水線 |
| 文件頁數(shù)： | 6/24頁 |
| 文件大?。?/td> | 244K |
| 代理商： | 7C1359A-150 |
CY7C1359A/GVT71256T18
Document #: 38-05120 Rev. **
Page 6 of 24
Notes:
7.
X means
“
Don
’
t Care.
”
H means logic HIGH. L means logic LOW. WRITE = L means [BWE + WEL*WEH]*GW equals LOW. WRITE = H means [BWE +
WEL*WEH]*GW equals HIGH. It is assumed in this truth table that DEN is LOW.
WEL enables write to DQ1
–
DQ9. WEH enables write to DQ10
–
DQ18.
All inputs except OE must meet set-up and hold times around the rising edge (LOW to HIGH) of CLK.
9.
11.
ADSP LOW along with chip being selected always initiates a READ cycle at the L-H edge of CLK. A WRITE cycle can be performed by setting WRITE LOW for
the CLK L-H edge of the subsequent wait cycle. Refer to WRITE timing diagram for clarification.
12. X means
“
don
’
t care.
”
H means logic HIGH. L means logic LOW. It is assumed in this truth table that chip is selected and ADSP is HIGH along with DEN being LOW.
8.
Truth Table
[5, 6, 7, 8, 9, 10, 11]
Operation
Address
Used
None
None
None
None
None
External
External
External
External
External
Next
Next
Next
Next
Next
Next
Current
Current
Current
Current
Current
Current
CE
H
L
L
L
L
L
L
L
L
L
X
X
H
H
X
H
X
X
H
H
X
H
CE2
X
X
H
X
H
L
L
L
L
L
X
X
X
X
X
X
X
X
X
X
X
X
CE2
X
L
X
L
X
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
ADSP
X
L
L
H
H
L
L
H
H
H
H
H
X
X
H
X
H
H
X
X
H
X
ADSC
L
X
X
L
L
X
X
L
L
L
H
H
H
H
H
H
H
H
H
H
H
H
ADV
X
X
X
X
X
X
X
X
X
X
L
L
L
L
L
L
H
H
H
H
H
H
WRITE
X
X
X
X
X
X
X
L
H
H
H
H
H
H
L
L
H
H
H
H
L
L
OE
X
X
X
X
X
L
H
X
L
H
L
H
L
H
X
X
L
H
L
H
X
X
CLK
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
DQ
High-Z
High-Z
High-Z
High-Z
High-Z
Q
High-Z
D
Q
High-Z
Q
High-Z
Q
High-Z
D
D
Q
High-Z
Q
High-Z
D
D
Deselected Cycle, Power Down
Deselected Cycle, Power Down
Deselected Cycle, Power Down
Deselected Cycle, Power Down
Deselected Cycle, Power Down
READ Cycle, Begin Burst
READ Cycle, Begin Burst
WRITE Cycle, Begin Burst
READ Cycle, Begin Burst
READ Cycle, Begin Burst
READ Cycle, Continue Burst
READ Cycle, Continue Burst
READ Cycle, Continue Burst
READ Cycle, Continue Burst
WRITE Cycle, Continue Burst
WRITE Cycle, Continue Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
WRITE Cycle, Suspend Burst
WRITE Cycle, Suspend Burst
Partial Truth Table for READ/WRITE
[12]
Function
GW
H
H
H
H
L
BWE
H
L
L
L
X
WEH
X
H
L
L
X
WEL
X
H
H
L
X
READ
READ
WRITE one byte
WRITE all bytes
WRITE all bytes
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