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參數(shù)資料
| 型號： | 7C1359A-150 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 256K x 18 Synchronous-Pipelined Cache Tag RAM |
| 中文描述： | 256 × 18的同步高速緩存標(biāo)記內(nèi)存流水線 |
| 文件頁數(shù)： | 13/24頁 |
| 文件大?。?/td> | 244K |
| 代理商： | 7C1359A-150 |
CY7C1359A/GVT71256T18
Document #: 38-05120 Rev. **
Page 13 of 24
Identification Register Definitions
Instruction Field
REVISION NUMBER
(31:28)
DEVICE DEPTH
(27:23)
DEVICE WIDTH
(22:18)
RESERVED
(17:12)
CYPRESS JEDEC ID CODE (11:1)
ID Register Presence
Indicator (0)
512K x 18
XXXX
Description
Reserved for revision number.
00111
Defines depth of 256K words.
00011
Defines width of x18 bits.
XXXXXX
Reserved for future use.
00011100100
1
Allows unique identification of DEVICE vendor.
Indicates the presence of an ID register.
Scan Register Sizes
Register Name
Bit Size
Instruction
3
Bypass
1
ID
32
Boundary Scan
54
Instruction Codes
Instruction
Code
000
Description
EXTEST
Captures I/O ring contents. Places the boundary scan register between TDI
and TDO. Forces all device outputs to High-Z state. This instruction is not
IEEE 1149.1-compliant.
Preloads ID register with vendor ID code and places it between TDI and
TDO. This instruction does not affect device operations.
Captures I/O ring contents. Places the boundary scan register between TDI
and TDO. Forces all device outputs to High-Z state.
Do not use these instructions; they are reserved for future use.
Captures I/O ring contents. Places the boundary scan register between TDI
and TDO. This instruction does not affect device operations. This instruction
does not implement IEEE 1149.1 PRELOAD function and is therefore not
1149.1-compliant.
Do not use these instructions; they are reserved for future use.
Do not use these instructions; they are reserved for future use.
Places the bypass register between TDI and TDO. This instruction does not
affect device operations.
IDCODE
001
SAMPLE-Z
010
RESERVED
SAMPLE/PRELOAD
011
100
RESERVED
RESERVED
BYPASS
101
110
111
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