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參數(shù)資料
| 型號(hào)： | 7C1359A-133 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 256K x 18 Synchronous-Pipelined Cache Tag RAM |
| 中文描述： | 256 × 18的同步高速緩存標(biāo)記內(nèi)存流水線 |
| 文件頁數(shù)： | 5/24頁 |
| 文件大?。?/td> | 244K |
| 代理商： | 7C1359A-133 |
CY7C1359A/GVT71256T18
Document #: 38-05120 Rev. **
Page 5 of 24
Notes:
2.
3.
4.
5.
X means
“
don
’
t care.
”
H means logic HIGH. L means logic LOW. It is assumed in this table that ADSP is HIGH and ADSC is LOW.
E=L is defined as CE=LOW and CE
=LOW and CE
=HIGH. E =H is defined as CE=HIGH or CE
=HIGH or CE
=LOW. WE is defined as [BWE + WEL*WEH]*GW.
All inputs except OE and MOE must meet setup and hold times around the rising edge (LOW to HIGH) of CLK.
For a write operation following a read operation, OE must be HIGH before the input data required setup time plus High-Z time for OE and staying HIGH throughout
the input data hold time.
This device contains circuitry that will ensure the outputs will be in High-Z during power-up.
6.
6P
51
MOE
Input
Match Output Enable: This active LOW asynchronous input
enables the MATCH output drivers.
Data Inputs/Outputs: Input data must meet setup and hold
times around the rising edge of CLK.
7P, 6N, 6L, 7K,
6H, 7G, 6F, 7E,
6D, 1D, 2E, 2G,
1H, 2K, 1L, 2M,
1N, 2P
5U
2U
3U
4U
4C, 2J, 4J, 6J, 4R
3D, 5D, 3E, 5E,
3F, 5F, 5G, 3H,
5H, 3K, 5K, 3L,
3M, 5M, 3N, 5N,
3P, 5P
1A, 7A, 1F, 7F, 1J,
7J, 1M, 7M, 1U,
7U
1B, 7B, 1C, 7C,
2D, 4D, 7D, 1E,
6E, 2F, 1G, 6G,
2H, 7H, 3J, 5J,
1K, 6K, 2L, 4L,
7L, 2N, 1P, 1R,
5R, 7R, 1T, 4T, 6U
58, 59, 62, 63, 68,
69, 72, 73, 74, 8,
9, 12, 13, 18, 19,
22, 23, 24
DQ1
–
DQ18
Input/
Output
42
38
39
43
TDO
TMS
TDI
TCK
V
CC
V
SS
Output
Input
IEEE 1149.1 test output. LVTTL-level output.
IEEE 1149.1 test inputs. LVTTL-level inputs.
15, 41,65, 91
5, 10, 17, 21, 26,
40, 55, 60, 67, 71,
76, 90
Supply
Ground
Power Supply: +3.3V
–
5% and +10%
Ground: GND
4, 11, 20, 27, 54,
61, 70, 77
V
CCQ
I/O Supply
Output Buffer Supply: +2.5V (from 2.375V to V
CC
)
1-3, 6, 7, 14, 16,
25, 28-30, 56, 57,
66, 75, 78, 79, 95,
96
NC
-
No Connect: These signals are not internally connected.
Pin Descriptions
(continued)
BGA Pins
TQFP Pins
Name
Type
Description
Burst Address Table (MODE = NC/V
CC
)
First
Address
(external)
(internal)
A...A00
A...A01
A...A01
A...A00
A...A10
A...A11
A...A11
A...A10
Second
Address
Third
Address
(internal)
A...A10
A...A11
A...A00
A...A01
Fourth
Address
(internal)
A...A11
A...A10
A...A01
A...A00
Burst Address Table (MODE = GND)
First
Address
(external)
A...A00
A...A01
A...A10
A...A11
Second
Address
(internal)
A...A01
A...A10
A...A11
A...A00
Third
Address
(internal)
A...A10
A...A11
A...A00
A...A01
Fourth
Address
(internal)
A...A11
A...A00
A...A01
A...A10
Partial Truth Table for MATCH
[2, 3, 4, 5, 6]
Operation
E
L
L
L
L
H
H
WE
H
L
L
H
X
X
DEN
X
L
H
L
X
X
MOE
X
X
X
L
L
H
OE
L
H
H
H
X
X
MATCH
-
-
-
Output
H
High-Z
DQ
Q
D
High-Z
D
High-Z
High-Z
READ Cycle
WRITE Cycle
Fill WRITE Cycle
COMPARE Cycle
Deselected Cycle (MATCH Out)
Deselected Cycle
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