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| 型號： | 78Q8430STEM#DB |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 7/88頁 |
| 文件大?。?/td> | 0K |
| 描述： | EVAL BOARD 78Q8430 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | * |
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DS_8430_001
78Q8430 Data Sheet
Rev. 1.2
15
3.2.6
GBI Address Pins
Table 7: GBI Address Pin Descriptions
Signal
Pin Number
Type
Description
ADDR9
25
I
Address Bus
The address lines are required to be stable for the entire duration
of a
CS cycle. In synchronous bus mode, the address pins are
sampled on the first rising edge of BUSCLK that
CS is asserted
low. In asynchronous bus mode, the address pins are sampled as
soon as the falling edge of
CS is synchronized to the internal
system clock.
In 32-bit bus mode, ADDR[1:0] are ignored. In 16-bit bus mode,
ADDR[0] is ignored. In 8-bit bus mode, all ADDR bits are used to
reference a register byte.
ADDR8
24
I
ADDR7
23
I
ADDR6
22
I
ADDR5
21
I
ADDR4
20
I
ADDR3
19
I
ADDR2
18
I
ADDR1
9
I
ADDR0
10
I
3.2.7
GBI Control Pins
Table 8: GBI Control Pin Descriptions
Signal
Pin Number
Type
Description
RESET
7
I
Reset (active low)
Referred to as hardware reset. Causes all 78Q8430 outputs to
enter a high-impedance state, stops all current operations and
initializes registers.
CS
16
I
Chip Select (active low)
The Processor asserts this signal to initiate a read or write
operation.
WR
11
I
Write Enable (active low)
The Processor asserts
WR to indicate a write operation.
OE
12
I
Output Enable (active low)
The Processor asserts
OE to enable the 78Q8430 data drivers
during a read cycle.
MEMWAIT
13
OZ
Memory Wait
During a bus cycle the 78Q8430 asserts MEMWAIT to indicate
that it is not ready to drive or receive valid data on the DATA
lines. The polarity is dependent on the WAITMODE pin. When
WAITMODE is high then the pin is asserted high; when
WAITMODE is low then the pin is asserted low.
INT
72
OD
Interrupt (active low)
The 78Q8430 asserts the
INT signal low when it detects an
interrupt event.
PME
73
OD
Power Management Event (active low)
The 78Q8430 asserts the
PME signal low when it detects a
wake-up event.
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