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參數(shù)資料
| 型號： | 78Q8430-ARM9-EVM |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 31/88頁 |
| 文件大?。?/td> | 0K |
| 描述： | EVALUATION MODULE 78Q8430 ARM9 |
| 產品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 1 |
| 系列： | * |
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DS_8430_001
78Q8430 Data Sheet
Rev. 1.2
37
STEP 2. Write address and mask byte [1] through byte [4] to the CAM. For each byte the CAM rule
indicated by table 5.7.2 based on the filter number and byte number should be written as follows.
Reg.
Field
Value to write
CAR
ADDR
byte [1]:
byte [2]:
byte [3]:
byte [4]:
0x64+N
0x60+N
0x4C+N
0x48+N
RMR
Data Match
Value of MAC address byte [1] … byte [4]
Data Mask
Value of mask byte [1] . . . byte [4]
Previous Hit Match
Value of the CAM rule used by the previous byte
1
Previous Hit Mask
0x7F
RCR
Byte Offset
Retain default: 0x00
Interrupt
Retain default: 0
Control Logic Action
Retain default: NOP
2
Match Control
Retain default: MD
1As an example, the Previous Hit Match fields for filter #1 would be 0x7D, 0x65, 0x61 and 0x4D, for
byte [1] through byte [4] respectively.
2
Reg.
An exception is byte [4] of the broadcast filter. Multicast filter #3, byte [4] should have the Control
Logic Action field set to TAX.
STEP 3. Write address and mask byte [5] to CAM rule 0x3C+N as follows.
Field
Value to write
CAR
ADDR
0x3C+N
RMR
Data Match
Value of MAC address byte [5]
Data Mask
Value of mask byte [5]
Previous Hit Match
Set to the CAM rule that was used for byte [4] (0x48+N).
Previous Hit Mask
0x7F
RCR
Byte Offset
Retain default: 0x00
Interrupt
Retain default: 0
Control Logic Action
Set to TAX
1
Match Control
Retain default: MD
1
It is important that STEP 1 deactivates the filter so that no frames are filtered using a partial filter setting
before all relevant rules are written. STEP 4 reactivates the filter once the new settings are in place.
Exception: Multicast filter #3, byte [5] should have the Action field set to SETBC.
STEP 4. Enable the filter. The multicast address filter is enabled by setting the Previous Hit Mask field of the
CAM rule for byte [0] to 0x7F. This step must be done last to prevent an ingressing frame from
matching a partial set of filter rules. All the rules for a filter must be in place before enabling the filter.
A Multicast address filter can be simply activated/deactivated by toggling the value of the Previous Hit
Mask field for the byte [0] CAM rule between 0x7F and 0x00 respectively. Multicast filter #0 should not be
deactivated in this way.
6.7.1.5
Negative Address Filters
Any address filter, either multicast or unicast, can be set as either a positive or negative filter. A positive
filter is a filter that passes frames with a source MAC address that matches the filter. A negative filter is a
filter that blocks frames with a source MAC address that matches the filter. By default, all filters are
positive acting. The following procedure is used to change a filter to negative action:
STEP 1. Change the Match Control field for the CAM rule for byte [5] from MD to DROP.
To change a filter back to a positive acting filter, change the same Match Control field back to MD.
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| 78-R3 | 功能描述:3M SCOTCHCAST REENTERABLE SIGNAL 制造商:3m 系列:* 零件狀態(tài):在售 標準包裝:1 |
| 78-R4 | 功能描述:3M SCOTCHCAST REENTERABLE SIGNAL 制造商:3m 系列:* 零件狀態(tài):在售 標準包裝:1 |
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