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| 型號(hào)： | 7540 |
| 英文描述： | 250MA CMOS LDO, ISUPPLY 1UA & 2% VOUT ACCURACY, -40C to +125C, 3-SOT-89, T/R |
| 中文描述： | 7540群用戶手冊(cè)數(shù)據(jù)4267K/MAY.28.03 |
| 文件頁(yè)數(shù)： | 43/365頁(yè) |
| 文件大小： | 4267K |
| 代理商： | 7540 |
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HARDWARE
7540 Group User
’
s Manual
1-25
(3) Event counter mode
Timer A counts signals input from the P0
0
/CNTR
1
pin.
Except for this, the operation in event counter mode is the same
as in timer mode.
The active edge of CNTR
1
pin input signal can be selected from
rising or falling by the CNTR
1
active edge switch bit .
(4) Pulse width HL continuously measurement mode
In the pulse width HL continuously measurement mode, the pulse
width (
“
H
”
and
“
L
”
levels) input to the P0
0
/CNTR
1
pin is measured.
CNTR
1
interrupt request is generated at both rising and falling
edges of CNTR
1
pin input signal. Except for this, the operation in
pulse width HL continuously measurement mode is the same as in
period measurement mode.
The count value when trigger input from the CNTR
1
pin is ac-
cepted is retained until Timer A is read once.
Timer A can stop counting by setting
“
1
”
to the timer A count stop
bit in any mode.
Also, when Timer A underflows, the timer A interrupt request bit is
set to
“
1
”
.
Note on Timer A is described below;
I
Note on Timer A
CNTR
1
interrupt active edge selection
CNTR
1
interrupt active edge depends on the CNTR
1
active edge
switch bit.
When this bit is
“
0
”
, the CNTR
1
interrupt request bit is set to
“
1
”
at
the falling edge of the CNTR
1
pin input signal. When this bit is
“
1
”
,
the CNTR
1
interrupt request bit is set to
“
1
”
at the rising edge of
the CNTR
1
pin input signal.
However, in the pulse width HL continuously measurement mode,
CNTR
1
interrupt request is generated at both rising and falling
edges of CNTR
1
pin input signal regardless of the setting of
CNTR
1
active edge switch bit.
Fig. 22 Structure of timer A mode register
Timer A mode register
(TAM : address 001D
16
, initial value: 00
16
)
b7
b0
Not used (return
“
0
”
when read)
Timer A operating mode bits
b5 b4
0 0 : Timer mode
0 1 : Period measurement mode
1 0 : Event counter mode
1 1 : Pulse width HL continuously
measurement mode
CNTR
1
active edge switch bit
0 : Count at rising edge in event counter mode
Measure the falling edge period in period
measurement mode
Falling edge active for CNTR
1
interrupt
1 : Count at falling edge in event counter mode
Measure the rising edge period in period
measurement mode
Rising edge active for CNTR
1
interrupt
Timer A count stop bit
0 : Count start
1 : Count stop
G
Timer X
Timer X is an 8-bit timer and counts the prescaler X output.
When Timer X underflows, the timer X interrupt request bit is set
to
“
1
”
.
Prescaler X is an 8-bit prescaler and counts the signal selected by
the timer X count source selection bit.
Prescaler X and Timer X have the prescaler X latch and the timer
X latch to retain the reload value, respectively. The value of
prescaler X latch is set to Prescaler X when Prescaler X
underflows.The value of timer X latch is set to Timer X when Timer
X underflows.
When writing to Prescaler X (PREX) is executed, the value is writ-
ten to both the prescaler X latch and Prescaler X.
When writing to Timer X (TX) is executed, the value is written to
both the timer X latch and Timer X.
When reading from Prescaler X (PREX) and Timer X (TX) is ex-
ecuted, each count value is read out.
Timer X can can be selected in one of 4 operating modes by set-
ting the timer X operating mode bits of the timer X mode register.
(1) Timer mode
Prescaler X counts the count source selected by the timer X count
source selection bits. Each time the count clock is input, the con-
tents of Prescaler X is decremented by 1. When the contents of
Prescaler X reach
“
00
16
”
, an underflow occurs at the next count
clock, and the prescaler X latch is reloaded into Prescaler X and
count continues. The division ratio of Prescaler X is 1/(n+1) pro-
vided that the value of Prescaler X is n.
The contents of Timer X is decremented by 1 each time the under-
flow signal of Prescaler X is input. When the contents of Timer X
reach
“
00
16
”
, an underflow occurs at the next count clock, and the
timer X latch is reloaded into Timer X and count continues. The di-
vision ratio of Timer X is 1/(m+1) provided that the value of Timer
X is m. Accordingly, the division ratio of Prescaler X and Timer X is
1/((n+1)
(m+1)) provided that the value of Prescaler X is n and
the value of Timer X is m.
(2) Pulse output mode
In the pulse output mode, the waveform whose polarity is inverted
each time timer X underflows is output from the CNTR
0
pin.
The output level of CNTR
0
pin can be selected by the CNTR
0
ac-
tive edge switch bit. When the CNTR
0
active edge switch bit is
“
0
”
,
the output of CNTR
0
pin is started at
“
H
”
level. When this bit is
“
1
”
,
the output is started at
“
L
”
level.
Also, the inverted waveform of pulse output from CNTR
0
pin can
be output from TX
OUT
pin by setting
“
1
”
to the P0
3
/TX
OUT
output
valid bit.
When using a timer in this mode, set the port P1
4
and P0
3
direc-
tion registers to output mode.
(3) Event counter mode
The timer A counts signals input from the P1
4
/CNTR
0
pin.
Except for this, the operation in event counter mode is the same
as in timer mode.
The active edge of CNTR
0
pin input signal can be selected from
rising or falling by the CNTR
0
active edge switch bit .
FUNCTIONAL DESCRIPTION
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