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參數(shù)資料
| 型號(hào)： | 74LV107PW |
| 廠(chǎng)商： | NXP SEMICONDUCTORS |
| 元件分類(lèi)： | 通用總線(xiàn)功能 |
| 英文描述： | CLP SINE |
| 中文描述： | LV/LV-A/LVX/H SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14 |
| 封裝： | 4.40 MM, PLASTIC, MO-153, SOT-402-1, TSSOP1-14 |
| 文件頁(yè)數(shù)： | 2/12頁(yè) |
| 文件大小： | 121K |
| 代理商： | 74LV107PW |
Philips Semiconductors
Product specification
74LV107
Dual JK flip-flop with reset; negative-edge trigger
2
1998 Apr 20
853–1904 19255
FEATURES
Wide operating: 1.0 to 5.5 V
Optimized for low voltage applications: 1.0 to 3.6 V
Accepts TTL input levels between V
CC
= 2.7 V and V
CC
= 3.6 V
Typical V
OLP
(output ground bounce) < 0.8 V at V
CC
= 3.3 V,
T
amb
= 25
°
C
Typical V
OHV
(output V
OH
undershoot) > 2 V at V
CC
= 3.3 V,
T
amb
= 25
°
C
Output capability: standard
I
CC
category: flip-flops
DESCRIPTION
The 74LV107 is a low-voltage Si-gate CMOS device that is pin and
function compatible with 74HC/HCT107.
The 74LV107 is a dual negative-edge triggered JK-type flip-flop
featuring individual J, K, clock (nCP) and reset (nR) inputs; also
complementary Q and Q outputs.
The J and K inputs must be stable one set-up time prior to the
HIGH-to-LOW clock transition for predictable operation.
The reset (nR) is an asynchronous active LOW input. When LOW, it
overrides the clock and data inputs, forcing the Q output LOW and
the Q output HIGH.
Schmitt-trigger action in the clock input makes the circuit highly
tolerant to slower clock rise and fall times.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°
C; t
r
= t
f
≤
2.5 ns
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
t
PHL
/t
PLH
Propagation delay
nCP to nQ
nCP to nQ
nR to nQ, nQ
C
L
= 15 pF;
V
CC
= 3.3 V
15
15
15
ns
f
max
C
I
C
PD
Maximum clock frequency
77
MHz
Input capacitance
3.5
pF
Power dissipation capacitance per flip-flop
V
I
= GND to V
CC1
30
pF
NOTE:
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
μ
W)
P
D
= C
PD
×
V
CC2
×
f
i
(C
L
×
V
CC2
f
i
= input frequency in MHz; C
L
= output load capacitance in pF;
f
o
= output frequency in MHz; V
CC
= supply voltage in V;
(C
L
×
V
CC2
×
f
o
) = sum of the outputs.
f
o
) where:
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
OUTSIDE NORTH AMERICA
NORTH AMERICA
PKG. DWG. #
14-Pin Plastic DIL
–40
°
C to +125
°
C
74LV107 N
74LV107 N
SOT27-1
14-Pin Plastic SO
–40
°
C to +125
°
C
74LV107 D
74LV107 D
SOT108-1
14-Pin Plastic SSOP Type II
–40
°
C to +125
°
C
74LV107 DB
74LV107 DB
SOT337-1
14-Pin Plastic TSSOP Type I
–40
°
C to +125
°
C
74LV107 PW
74LV107PW DH
SOT402-1
PIN CONFIGURATION
SV00497
1J
1Q
1Q
1K
2Q
2Q
GND
1R
1CP
2K
2R
2CP
2J
14
13
12
11
10
9
8
1
2
3
4
5
6
7
V
CC
PIN DESCRIPTION
PIN
NUMBER
SYMBOL
FUNCTION
1, 8, 4, 11
1J, 2J, 1K, 2K
Synchronous inputs; flip-flops 1 and 2
2, 6
1Q, 2Q
Complement flip-flop outputs
3, 5
1Q, 2Q
True flip-flop outputs
7
GND
Ground (0 V)
12, 9
1CP, 2CP
Clock input
(HIGH-to-LOW, edge-triggered)
13, 10
1R, 2R
Asynchronous reset inputs
(active LOW)
14
V
CC
Positive supply voltage
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 74LV107PWDH | CLP SINE |
| 74LV109 | Dual JK flip-flop with set and reset; positive-edge trigger |
| 74LV109D | CMOS |
| 74LV109DB | Dual JK flip-flop with set and reset; positive-edge trigger |
| 74LV109N | CMOS/TTL Compatible |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 74LV107PWDH | 制造商:PHILIPS 制造商全稱(chēng):NXP Semiconductors 功能描述:Dual JK flip-flop with reset; negative-edge trigger |
| 74LV107PW-T | 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:J-K-Type Flip-Flop |
| 74LV109 | 制造商:PHILIPS 制造商全稱(chēng):NXP Semiconductors 功能描述:Dual JK flip-flop with set and reset; positive-edge trigger |
| 74LV109D | 制造商:PHILIPS 制造商全稱(chēng):NXP Semiconductors 功能描述:Dual JK flip-flop with set and reset; positive-edge trigger |
| 74LV109DB | 制造商:PHILIPS 制造商全稱(chēng):NXP Semiconductors 功能描述:Dual JK flip-flop with set and reset; positive-edge trigger |
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