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參數(shù)資料
| 型號(hào)： | 74LS194 |
| 廠(chǎng)商： | ON SEMICONDUCTOR |
| 英文描述： | LOW POWER SCHOTTKY |
| 中文描述： | 低功耗肖特基 |
| 文件頁(yè)數(shù)： | 5/8頁(yè) |
| 文件大?。?/td> | 135K |
| 代理商： | 74LS194 |
SN74LS194A
http://onsemi.com
5
AC SETUP REQUIREMENTS
(T
A
= 25
°
C)
Limits
Symbol
Parameter
Min
Typ
Max
Unit
Test Conditions
t
W
Clock or MR Pulse Width
20
ns
t
s
Mode Control Setup Time
30
ns
t
s
Data Setup Time
20
ns
V
CC
= 5.0 V
t
h
Hold time, Any Input
0
ns
t
rec
Recovery Time
25
ns
DEFINITIONS OF TERMS
SETUP TIME(t
s
) —is defined as the minimum time
required for the correct logic level to be present at the logic
input prior to the clock transition from LOW to HIGH in
order to be recognized and transferred to the outputs.
HOLD TIME (t
h
) — is defined as the minimum time
following the clock transition from LOW to HIGH that the
logic level must be maintained at the input in order to ensure
continued recognition. A negative HOLD TIME indicates
that the correct logic level may be released prior to the clock
transition from LOW to HIGH and still be recognized.
RECOVERY TIME (t
rec
) — is defined as the minimum time
required between the end of the reset pulse and the clock
transition from LOW to HIGH in order to recognize and
transfer HIGH Data to the Q outputs.
AC WAVEFORMS
The shaded areas indicate when the input is permitted to change for predictable output performance.
Figure 1. Clock to Output Delays Clock Pulse
Width and f
max
Figure 2. Master Reset Pulse Width, Master Reset
to Output Delay and Master Reset to Clock
Recovery Time
1.3 V
1.3 V
OTHER CONDITIONS: S
1
= L, MR = H, S
0
= H
OTHER CONDITIONS: S
0
, S
1
= H
OTHER CONDITIONS:
P
O
= P
1
= P
2
= P
3
= H
OTHER CONDITIONS: MR = H
OTHER CONDITIONS:
*D
SR
SET-UP TIME AFFECTS Q
0
ONLY
OTHER CONDITIONS:
D
SL
SET-UP TIME AFFECTS Q
3
ONLY
OTHER CONDITIONS: MR = H
S
0
S
1
D
SR
D
SL
P
0
P
1
P
2
P
3
CLOCK
OUTPUT*
(––– IS SHIFT LEFT)
CLOCK
CLOCK
CLOCK
OUTPUT
OUTPUT
S
0
S
1
t
s
(H)
t
h
(H) = 0
t
h
(L) = 0
t
h
(H) = 0
t
s
(H)
t
h
(L) = 0
t
s
(L)
t
h
= 0
t
h
= 0
(STABLE TIME)
t
PHL
t
PLH
1/fmax
t
W
t
s
(L)
MR
t
W
t
rec
t
PHL
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
t
s
t
s
Figure 3. Setup (t
s
) and Hold (t
h
) Time for Serial Data
(D
SR
, D
SL
) and Parallel Data (P
0
, P
1
, P
2
, P
3
)
Figure 4. Setup (t
s
) and Hold (t
h
) Time for S Input
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 74LS194 WAF | 制造商:Texas Instruments 功能描述: |
| 74LS194A | 制造商:NSC 制造商全稱(chēng):National Semiconductor 功能描述:4-Bit Bidirectional Universal Shift Register |
| 74LS194ADC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| 74LS194AN | 制造商:NXP Semiconductors 功能描述:Shift Register, 16 Pin, Plastic, DIP 制造商:Texas Instruments 功能描述:Shift Register, 16 Pin, Plastic, DIP |
| 74LS194APC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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