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參數(shù)資料
| 型號： | 74LS194 |
| 廠商： | ON SEMICONDUCTOR |
| 英文描述： | LOW POWER SCHOTTKY |
| 中文描述： | 低功耗肖特基 |
| 文件頁數(shù)： | 3/8頁 |
| 文件大小： | 135K |
| 代理商： | 74LS194 |
SN74LS194A
http://onsemi.com
3
LOGIC DIAGRAM
V
CC
= PIN 16
GND = PIN 8
= PIN NUMBERS
S
1
S
0
D
SR
D
SL
CP
MR
Q
0
Q
1
Q
2
Q
3
P
0
P
1
P
2
P
3
14
1
2
6
7
3
4
5
9
11
12
10
13
15
S
Q
0
CP
R
CLEAR
S
Q
1
CP
R
CLEAR
S
Q
2
CP
R
CLEAR
S
Q
3
CP
R
CLEAR
FUNCTIONAL DESCRIPTION
The Logic Diagram and Truth Table indicate the
functional characteristics of the LS194A 4-Bit Bidirectional
Shift Register. The LS194A is similar in operation to the
ON Semiconductor LS195A Universal Shift Register when
used in serial or parallel data register transfers. Some of the
common features of the two devices are described below:
All data and mode control inputs are edge-triggered,
responding only to the LOW to HIGH transition of the Clock
(CP). The only timing restriction, therefore, is that the mode
control and selected data inputs must be stable one set-up
time prior to the positive transition of the clock pulse.
The register is fully synchronous, with all operations
taking place in less than 15 ns (typical) making the device
especially useful for implementing very high speed CPUs,
or the memory buffer registers.
The four parallel data inputs (P
0
, P
1
, P
2
, P
3
) are D-type
inputs. When both S
0
and S
1
are HIGH, the data appearing
on P
0
, P
1
, P
2
, and P
3
inputs is transferred to the Q
0
, Q
1
, Q
2
,
and Q
3
outputs respectively following the next LOW to
HIGH transition of the clock.
The asynchronous Master Reset (MR), when LOW,
overrides all other input conditions and forces the Q outputs
LOW.
Special logic features of the LS194A design which
increase the range of application are described below:
Two mode control inputs (S
0
, S
1
) determine the
synchronous operation of the device. As shown in the Mode
Selection Table, data can be entered and shifted from left to
right (shift right, Q
0
Q
1
, etc.) or right to left (shift left, Q
3
Q
2
, etc.), or parallel data can be entered loading all four
bits of the register simultaneously. When both S
0
and S
1
,are
LOW, the existing data is retained in a “do nothing” mode
without restricting the HIGH to LOW clock transition.
D-type serial data inputs (D
SR
, D
SL
) are provided on both
the first and last stages to allow multistage shift right or shift
left data transfers without interfering with parallel load
operation.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 74LS194 | 4-Bit Bidirectional Universal Shift Register |
| 74LS197 | 4-STAGE PRESETTABLE RIPPLE COUNTERS |
| 74LS221 | LOW POWER SCHOTTKY |
| 74LS221N | LOW POWER SCHOTTKY |
| 74LS221N | DUAL MONOSTABLE MULTIVIBRATORS WITH SCHMITT-TRIGGER INPUTS |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 74LS194 WAF | 制造商:Texas Instruments 功能描述: |
| 74LS194A | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:4-Bit Bidirectional Universal Shift Register |
| 74LS194ADC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| 74LS194AN | 制造商:NXP Semiconductors 功能描述:Shift Register, 16 Pin, Plastic, DIP 制造商:Texas Instruments 功能描述:Shift Register, 16 Pin, Plastic, DIP |
| 74LS194APC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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