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參數(shù)資料
| 型號(hào)： | 74LS197 |
| 廠商： | Motorola, Inc. |
| 元件分類： | 通用總線功能 |
| 英文描述： | 4-STAGE PRESETTABLE RIPPLE COUNTERS |
| 中文描述： | 4級(jí)預(yù)置紋波計(jì)數(shù)器 |
| 文件頁(yè)數(shù)： | 1/8頁(yè) |
| 文件大?。?/td> | 227K |
| 代理商： | 74LS197 |
5-372
FAST AND LS TTL DATA
4-STAGE PRESETTABLE
RIPPLE COUNTERS
The SN54/74LS196 decade counter is partitioned into divide-by-two and di-
vide-by-five sections which can be combined to count either in BCD (8, 4, 2, 1)
sequence or in a bi-quinary mode producing a 50% duty cycle output. The
SN54/74LS197 contains divide-by-two and divide-by-eight sections which
can be combined to form a modulo-16 binary counter. Low Power Schottky
technology is used to achieve typical count rates of 70 MHz and power dis-
sipation of only 80 mW.
Both circuit types have a Master Reset (MR) input which overrides all other
inputs and asynchronously forces all outputs LOW. A Parallel Load input (PL)
overrides clocked operations and asynchronously loads the data on the Par-
allel Data inputs (Pn) into the flip-flops. This preset feature makes the circuits
usable as programmable counters. The circuits can also be used as 4-bit
latches, loading data from the Parallel Data inputs when PL is LOW and stor-
ing the data when PL is HIGH.
Low Power Consumption — Typically 80 mW
High Counting Rates — Typically 70 MHz
Choice of Counting Modes — BCD, Bi-Quinary, Binary
Asynchronous Presettable
Asynchronous Master Reset
Easy Multistage Cascading
Input Clamp Diodes Limit High Speed Termination Effects
CONNECTION DIAGRAM DIP
(TOP VIEW)
NOTE:
The Flatpak version
has the same pinouts
(Connection Diagram) as
the Dual In-Line Package.
PIN NAMES
LOADING
(Note a)
HIGH
LOW
CP0
Clock (Active LOW Going Edge)
Input to Divide-by-Two Section
Clock (Active LOW Going Edge)
Input to Divide-by-Five Section
Clock (Active LOW Going Edge)
Input to Divide-by-Eight Section
Master Reset (Active LOW) Input
Parallel Load (Active LOW) Input
Data Inputs
Outputs (Notes b, c)
1.0 U.L.
1.5 U.L.
CP1 (LS196)
2.0 U.L.
1.75 U.L.
CP1 (LS197)
1.0 U.L.
0.8 U.L.
MR
PL
P0–P3
Q0–Q3
NOTES:
a. 1 TTL Unit Load (U.L.) = 40
μ
A HIGH/1.6 mA LOW.
b. The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74)
b.
Temperature Ranges.
c. In addition to loading shown, Q0 can also drive CP1.
1.0 U.L.
0.5 U.L.
0.5 U.L.
10 U.L.
0.5 U.L.
0.25 U.L.
0.25 U.L.
5 (2.5) U.L.
SN54/74LS196
SN54/74LS197
4-STAGE PRESETTABLE
RIPPLE COUNTERS
LOW POWER SCHOTTKY
J SUFFIX
CERAMIC
CASE 632-08
N SUFFIX
PLASTIC
CASE 646-06
14
1
14
1
ORDERING INFORMATION
SN54LSXXXJ
SN74LSXXXN
SN74LSXXXD
Ceramic
Plastic
SOIC
14
1
D SUFFIX
SOIC
CASE 751A-02
LOGIC SYMBOL
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 74LS221 | LOW POWER SCHOTTKY |
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| 74LS221N | DUAL MONOSTABLE MULTIVIBRATORS WITH SCHMITT-TRIGGER INPUTS |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 74LS197N | 制造商: 功能描述: 制造商:undefined 功能描述: |
| 74LS197PC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Asynchronous Up Counter |
| 74LS20 | 制造商:NTE Electronics 功能描述: 制造商:Semiconductors 功能描述: |
| 74LS20 WAF | 制造商:Texas Instruments 功能描述: |
| 74LS20D | 制造商:North American Philips Discrete Products Div 功能描述:74LS20D |
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