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| 型號： | 74HCT9046A |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | PLL with bandgap controlled VCO |
| 中文描述： | 鎖相環(huán)控制VCO的帶隙 |
| 文件頁數(shù)： | 9/40頁 |
| 文件大?。?/td> | 240K |
| 代理商： | 74HCT9046A |
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1999 Jan 11
9
Philips Semiconductors
Product specification
PLL with bandgap controlled VCO
74HCT9046A
The pump current I
P
is independent
from the supply voltage and is set by
the internal bandgap reference of
2.5 V.
R
b
is the external bias resistor
between pin 15 and ground.
The current and voltage transfer
function of PC2 are shown in Fig.9.
The phase comparator gain is:
I
2
π
Typical waveforms for the PC2 loop
locked at f
c
are shown in Fig.10.
When the frequencies of SIG
IN
and
COMP
IN
are equal but the phase of
SIG
IN
leads that of COMP
IN
, the up
output driver at PC2
OUT
is held ‘ON’
for a time corresponding to the phase
difference (
Φ
PCIN
). When the phase of
SIG
IN
lags that of COMP
IN
, the down
or sink driver is held ‘ON’.
When the frequency of SIG
IN
is higher
than that of COMP
IN
, the source
output driver is held ‘ON’ for most of
the input signal cycle time and for the
remainder of the cycle time both
drivers are ‘OFF’ (3-state). If the
SIG
IN
frequency is lower than the
COMP
IN
frequency, then it is the sink
driver that is held ‘ON’ for most of the
cycle. Subsequently the voltage at the
capacitor (C2) of the low-pass filter
connected to PC2
OUT
varies until the
signal and comparator inputs are
equal in both phase and frequency. At
this stable point the voltage on C2
remains constant as the PC2 output is
in 3-state and the VCO input at pin 9
is a high impedance. Also in this
condition the signal at the phase
comparator pulse output (PCP
OUT
)
has a minimum output pulse width
equal to the overlap time, so can be
used for indicating a locked condition.
I
P
17
R
b
2.5
( )
×
=
K
p
------- A r
)
=
Thus for PC2 no phase difference
exists between SIG
IN
and COMP
IN
over the full frequency range of the
VCO. Moreover, the power
dissipation due to the low-pass filter is
reduced because both output drivers
are OFF for most of the signal input
cycle. It should be noted that the PLL
lock range for this type of phase
comparator is equal to the capture
range and is independent of the
low-pass filter. With no signal present
at SIG
IN
the VCO adjust, via PC2, to
its lowest frequency.
By using current sources as charge
pump output on PC2, the dead zone
or backlash time could be reduced to
zero. Also, the pulse widening due to
the parasitic output capacitance plays
no role here. This enables a linear
transfer function, even in the vicinity
of the zero crossing. The differences
between a voltage switch charge
pump and a current switch charge
pump are shown in Fig.11.
The design of the low-pass filter is
somewhat different when using
current sources. The external resistor
R3 is no longer present when using
PC2 as phase comparator. The
current source is set by R
b
. A simple
capacitor behaves as an ideal
integrator now, because the capacitor
is charged by a constant current. The
transfer function of the voltage switch
charge pump may be used. In fact it is
even more valid, because the transfer
function is no longer restricted for
small changes only. Further the
current is independent from both the
supply voltage and the voltage across
the filter. For one that is familiar with
the low-pass filter design of the
4046A a relation may show how R
b
relates with a fictive series resistance,
called R3'.
This relation can be derived by
assuming first that a voltage
controlled switch PC2 of the 4046A is
connected to the filter capacitance C2
via this fictive R3' (see Fig.8b). Then
during the PC2 output pulse the
charge current equals:
V
V
–
With the initial voltage V
C2(0)
at:
1
2
V
CC
= 2.5 V,
As shown before the charge current
of the current switch of the 9046A is:
R
b
Hence:
Using this equivalent resistance R3'
for the filter design the voltage can
now be expressed as a transfer
function of PC2; assuming ripple
(f
r
= f
i
) is suppressed, as:
4
π
Again this illustrates the supply
voltage independent behaviour of
PC2.
Examples of PC2 combined with a
passive filter are shown in Figs 12
and 13. Figure 12 shows that PC2
with only a C2 filter behaves as a
high-gain filter. For stability the
damped version of Fig.13 with series
resistance R4 is preferred.
Practical design values for R
b
are
between 25 and 250 k
with
R3' = 1.5 to 15 k
for the filter design.
Higher values for R3' require lower
values for the filter capacitance which
is very advantageous at low values
the loop natural frequency
ω
n
.
I
P
-------------R3'
=
I
P
R3'
2.5
=
I
P
17
2.5
×
=
R3'
R
b
17
------
(
)
=
K
PC2
--5
(
)
=
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 74HCT9046AD | 功能描述:鎖相環(huán) - PLL PHASE LOCKED LOOP W/VCO RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| 74HCT9046AD,112 | 功能描述:鎖相環(huán) - PLL PHASE LOCKED LOOP RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| 74HCT9046AD,118 | 功能描述:鎖相環(huán) - PLL PLL BAND GAP CNTRL W/VCO RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| 74HCT9046AD-T | 制造商:PHILIPS-SEMI 功能描述: |
| 74HCT9046AN,112 | 功能描述:鎖相環(huán) - PLL PLL BAND GAP CNTRL W/VCO RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
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