參數(shù)資料
型號: 74HCT9046A
廠商: NXP Semiconductors N.V.
英文描述: PLL with bandgap controlled VCO
中文描述: 鎖相環(huán)控制VCO的帶隙
文件頁數(shù): 7/40頁
文件大小: 240K
代理商: 74HCT9046A
1999 Jan 11
7
Philips Semiconductors
Product specification
PLL with bandgap controlled VCO
74HCT9046A
Phase comparators
The signal input (SIG
IN
) can be
directly coupled to the self-biasing
amplifier at pin 14, provided that the
signal swing is between the standard
HC family input logic levels.
Capacitive coupling is required for
signals with smaller swings.
P
HASE COMPARATOR
1 (PC1)
This circuit is an EXCLUSIVE-OR
network. The signal and comparator
input frequencies (f
i
) must have a
50% duty factor to obtain the
maximum locking range. The transfer
characteristic of PC1, assuming
ripple (f
r
= 2f
i
) is suppressed, is:
where:
V
DEMOUT
is the demodulator output
at pin 10.
V
DEMOUT
= V
PC1OUT
(via low-pass).
The phase comparator gain is:
V
The average output voltage from
PC1, fed to the VCO input via the
low-pass filter and seen at the
demodulator output at pin 10
(V
DEMOUT
), is the resultant of the
phase differences of signals (SIG
IN
)
and the comparator input (COMP
IN
)
as shown in Fig.6. The average of
V
DEMOUT
is equal to
1
2
V
CC
when
there is no signal or noise at SIG
IN
and with this input the VCO oscillates
at the centre frequency (f
c
). Typical
waveforms for the PC1 loop locked at
f
c
are shown in Fig.7. This figure also
shows the actual waveforms across
the VCO capacitor at pins 6 and 7
(V
C1A
and V
C1B
) to show the relation
between these ramps and the
VCO
OUT
voltage.
V
DEMOUT
V
----------
Φ
SIGIN
Φ
COMPIN
(
)
=
K
p
---------- V r
)
=
The frequency capture range (2f
c
) is
defined as the frequency range of
input signals on which the PLL will
lock if it was initially out-of-lock. The
frequency lock range (2f
L
) is defined
as the frequency range of the input
signals on which the loop will stay
locked if it was initially in lock. The
capture range is smaller or equal to
the lock range.
With PC1, the capture range depends
on the low-pass filter characteristics
and can be made as large as the lock
range. This configuration remains
locked even with very noisy input
signals. Typical behaviour of this type
of phase comparator is that it may
lock to input frequencies close to the
harmonics of the VCO centre
frequency.
P
HASE COMPARATOR
2 (PC2)
This is a positive edge-triggered
phase and frequency detector. When
the PLL is using this comparator, the
loop is controlled by positive signal
transitions and the duty factors of
SIG
IN
and COMP
IN
are not important.
PC2 comprises two D-type flip-flops,
control gating and a 3-state output
stage with sink and source transistors
acting as current sources, henceforth
called charge pump output of PC2.
The circuit functions as an up-down
counter (Fig.5) where SIG
IN
causes
an up-count and COMP
IN
a down
count. The current switch charge
pump output allows a virtually ideal
performance of PC2, due to appliance
of some pulse overlap of the up and
down signals. See Fig.8a.
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