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參數(shù)資料
| 型號： | 74HCT9046A |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | PLL with bandgap controlled VCO |
| 中文描述： | 鎖相環(huán)控制VCO的帶隙 |
| 文件頁數(shù)： | 25/40頁 |
| 文件大?。?/td> | 240K |
| 代理商： | 74HCT9046A |
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1999 Jan 11
25
Philips Semiconductors
Product specification
PLL with bandgap controlled VCO
74HCT9046A
Fig.28 Typical power dissipation.
10
3
MBD109
10
2
10
10
4
PDEM
(W)
Rs
)
VCC
4.5 V
5.5 V
10
5
10
3
APPLICATION INFORMATION
This information is a guide for the approximation of values
of external components to be used with the 74HCT9046A
in a phase-locked-loop system.
Values of the selected components should be within the
rages shown in Table 2.
Table 2
Survey of components.
COMPONENT
VALUE
R1
R2
R1 + R2
C1
between 3 k
and 300 k
between 3 k
and 300 k
parallel value >2.7 k
>40 pF
Table 3
Design considerations for VCO section.
SUBJECT
PHASE
COMPARATOR
DESIGN CONSIDERATION
VCO frequency
without
extra offset
PC1, PC2
VCO frequency characteristic
With R2 =
∞
and R1 within the range 3 k
<
R1
<
300 k
, the
characteristics of the VCO operation will be as shown in Fig.29a.
(Due to R1, C1 time constant a small offset remains when R2 =
∞
).
Selection of R1 and C1
Given f
c
, determine the values of R1 and C1 using Fig.31.
Given f
max
and f
c
determine the values of R1 and C1 using Fig.31; use
Fig.33 to obtain 2f
L
and then use this to calculate f
min
.
VCO frequency characteristic
With R1 and R2 within the ranges 3 k
<
R1
<
300 k
<
R2
<
300 k
,
the characteristics of the VCO operation is as shown in Fig.29b.
Selection of R1, R2 and C1
Given f
c
and f
L
determine the value of product R1C1 by using Fig.33.
Calculate f
off
from the equation f
off
= f
c
1.6f
L
.
Obtain the values of C1 and R2 by using Fig.32.
Calculate the value of R1 from the value of C1 and the product R1C1.
VCO adjusts to f
c
with
Φ
PCIN
= 90
°
and V
VCOIN
=
1
2
V
CC
.
VCO adjusts to f
offset
with
Φ
PCIN
=
360
°
and V
VCOIN
= minimum.
PC1
PC2
VCO frequency
with extra offset
PC1, PC2
PC1, PC2
PLL conditions with no
signal at the SIG
IN
input
PC1
PC2
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 74HCT9046AD | 功能描述:鎖相環(huán) - PLL PHASE LOCKED LOOP W/VCO RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| 74HCT9046AD,112 | 功能描述:鎖相環(huán) - PLL PHASE LOCKED LOOP RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| 74HCT9046AD,118 | 功能描述:鎖相環(huán) - PLL PLL BAND GAP CNTRL W/VCO RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| 74HCT9046AD-T | 制造商:PHILIPS-SEMI 功能描述: |
| 74HCT9046AN,112 | 功能描述:鎖相環(huán) - PLL PLL BAND GAP CNTRL W/VCO RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
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