參數(shù)資料
型號(hào)： 74HC7046A
廠商： NXP Semiconductors N.V.
英文描述： Phase-locked-loop with lock detector
中文描述： 鎖相回路鎖定探測(cè)器
文件頁(yè)數(shù)： 2/38頁(yè)
文件大?。?/td> 490K
代理商： 74HC7046A
December 1990
2
Philips Semiconductors
Product specification
Phase-locked-loop with lock detector
74HC/HCT7046A
FEATURES
Low power consumption
Centre frequency up to 17 MHz
(typ.) at V
CC
= 4.5 V
Choice of two phase comparators:
EXCLUSIVE-OR;
edge-triggered JK flip-flop;
Excellent VCO frequency linearity
VCO-inhibit control for ON/OFF
keying and for low standby power
consumption
Minimal frequency drift
Operation power supply voltage
range:
VCO section 3.0 to 6.0 V
digital section 2.0 to 6.0 V
Zero voltage offset due to op-amp
buffering
Output capability: standard
I
CC
category: MSI
GENERAL DESCRIPTION
The 74HC/HCT7046 are high-speed
Si-gate CMOS devices and are
specified in compliance with JEDEC
standard no. 7.
The 74HC/HCT7046 are
phase-locked-loop circuits that
comprise a linear voltage-controlled
oscillator (VCO) and two different
phase comparators (PC1 and PC2)
with a common signal input amplifier
and a common comparator input.
A lock detector is provided and this
gives a HIGH level at pin 1 (LD) when
the PLL is locked. The lock detector
capacitor must be connected
between pin 15 (C
LD
) and pin 8
(GND). The value of the C
LD
capacitor
can be determined, using information
supplied in Fig.32. The input signal
can be directly coupled to large
voltage signals, or indirectly coupled
(with a series capacitor) to small
voltage signals. A self-bias input
circuit keeps small voltage signals
within the linear region of the input
amplifiers. With a passive low-pass
filter, the “7046” forms a second-order
loop PLL. The excellent VCO linearity
is achieved by the use of linear
op-amp techniques.
VCO
The VCO requires one external
capacitor C1 (between C1
A
and C1
B
)
and one external resistor R1
(between R
1
and GND) or two
external resistors R1 and R2
(between R
1
and GND, and R
2
and
GND). Resistor R1 and capacitor C1
determine the frequency range of the
VCO. Resistor R2 enables the VCO
to have a frequency offset if required.
The high input impedance of the VCO
simplifies the design of low-pass
filters by giving the designer a wide
choice of resistor/capacitor ranges. In
order not to load the low-pass filter, a
demodulator output of the VCO input
voltage is provided at pin 10
(DEM
OUT
). In contrast to conventional
techniques where the DEM
OUT
voltage is one threshold voltage lower
than the VCO input voltage, here the
DEM
OUT
voltage equals that of the
VCO input. If DEM
OUT
is used, a load
resistor (R
S
) should be connected
from DEM
OUT
to GND; if unused,
DEM
OUT
should be left open. The
VCO output (VCO
OUT
) can be
connected directly to the comparator
input (COMP
IN
), or connected via a
frequency-divider. The VCO output
signal has a duty factor of 50%
(maximum expected deviation 1%), if
the VCO input is held at a constant
DC level. A LOW level at the inhibit
input (INH) enables the VCO and
demodulator, while a HIGH level turns
both off to minimize standby power
consumption.
The only difference between the HC
and HCT versions is the input level
specification of the INH input. This
input disables the VCO section. The
comparators’ sections are identical,
so that there is no difference in the
SIG
IN
(pin 14) or COMP
IN
(pin 3)
inputs between the HC and HCT
versions.
Phase comparators
The signal input (SIG
IN
) can be
directly coupled to the self-biasing
amplifier at pin 14, provided that the
signal swing is between the standard
HC family input logic levels.
Capacitive coupling is required for
signals with smaller swings.
Phase comparator 1 (PC1)
This is an EXCLUSIVE-OR network.
The signal and comparator input
frequencies (f
i
) must have a 50% duty
factor to obtain the maximum locking
range. The transfer characteristic of
PC1, assuming ripple (f
r
= 2f
i
) is
suppressed,
is:
V
where V
DEMOUT
is the demodulator
output at pin 10;
V
DEMOUT
= V
PC1OUT
(via low-pass
filter).
The phase comparator gain
is:
V
The average output voltage from
PC1, fed to the VCO input via the
low-pass filter and seen at the
demodulator output at pin 10
(V
DEMOUT
), is the resultant of the
phase differences of signals (SIG
IN
)
and the comparator input (COMP
IN
)
as shown in Fig.6. The average of
V
DEMOUT
is equal to 1/2 V
CC
when
there is no signal or noise at SIG
IN
and with this input the VCO oscillates
at the centre frequency (f
o
). Typical
V
DEMOUT
----------
φ
SIGIN
φ
COMPIN
–
(
)
=
K
p
----------
V r
(
)
.
=
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
74HC7046AD 功能描述:鎖相環(huán) - PLL PHASE LOCKED LOOP W/DETECTOR RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray
74HC7046AD,112 功能描述:鎖相環(huán) - PLL PHASE LOCKED LOOP RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray
74HC7046AD,118 功能描述:鎖相環(huán) - PLL PHASE LOCKED LOOP RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray
74HC7046AD/AUJ 制造商:NXP Semiconductors 功能描述:2500 制造商:NXP Semiconductors 功能描述:74HC7046AD/SO16/REEL13//AU - Tape and Reel 制造商:NXP Semiconductors 功能描述:IC PLL W/LOCK DETECTOR 16SOIC 制造商:NXP Semiconductors 功能描述:Phase Locked Loops - PLL Phase-locked-loop w/lock detector
74HC7046ADB 功能描述:鎖相環(huán) - PLL PHASE LOCKED LOOP W/DETECTOR RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray
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