參數(shù)資料
型號: 74HC109PW
廠商: NXP SEMICONDUCTORS
元件分類: 通用總線功能
英文描述: Dual JK flip-flop with set and reset; positive-edge trigger
中文描述: HC/UH SERIES, DUAL POSITIVE EDGE TRIGGERED J-KBAR FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16
文件頁數(shù): 7/9頁
文件大小: 65K
代理商: 74HC109PW
1997 Nov 25
7
Philips Semiconductors
Product specification
Dual JK flip-flop with set and reset;
positive-edge trigger
74HC/HCT109
AC WAVEFORMS
Fig.6
Waveforms showing the clock (nCP) to output (nQ, nQ) propagation delays, the clock pulse width, the nJ,
nK to nCP set-up, the nCP to nJ, nK hold times, the output transition times and the maximum clock pulse
frequency.
The shaded areas indicate when the
input is permitted to change for
predictable output performance.
handbook, full pagewidth
MBK216
VM
(1)
nCP INPUT
nSD INPUT
nRD INPUT
nQ OUTPUT
nQ OUTPUT
VM
(1)
VM
(1)
VM
(1)
VM
(1)
tW
trem
trem
tW
tPHL
tPLH
tPLH
tPHL
Fig.7
Waveforms showing the set (nS
D
) and reset (nR
D
) input to output (nQ, nQ) propagation delays, the set
and reset pulse widths and the nR
D
, nS
D
to nCP removal time.
(1) HC: V
M
= 50%; V
I
= GND to V
.
HCT: V
M
= 1.3 V; V
I
= GND to 3 V.
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