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參數(shù)資料
| 型號： | 74HC109PW |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 通用總線功能 |
| 英文描述： | Dual JK flip-flop with set and reset; positive-edge trigger |
| 中文描述： | HC/UH SERIES, DUAL POSITIVE EDGE TRIGGERED J-KBAR FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16 |
| 文件頁數(shù)： | 2/9頁 |
| 文件大?。?/td> | 65K |
| 代理商： | 74HC109PW |
1997 Nov 25
2
Philips Semiconductors
Product specification
Dual JK flip-flop with set and reset;
positive-edge trigger
74HC/HCT109
FEATURES
J, K inputs for easy D-type flip-flop
Toggle flip-flop or “do nothing” mode
Output capability: standard
I
CC
category: flip-flops
GENERAL DESCRIPTION
The 74HC/HCT109 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT109 are dual positive-edge triggered, JK
flip-flops with individual J, K inputs, clock (CP) inputs, set
(S
D
) and reset (R
D
) inputs; also complementary Q and Q
outputs.
The set and reset are asynchronous active LOW inputs
and operate independently of the clock input.
The J and K inputs control the state changes of the
flip-flops as described in the mode select function table.
The J and K inputs must be stable one set-up time prior to
the LOW-to-HIGH clock transition for predictable
operation.
The JK design allows operation as a D-type flip-flop by
tying the J and K inputs together.
Schmitt-trigger action in the clock input makes the circuit
highly tolerant to slower clock rise and fall times.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°
C; t
r
= t
f
= 6 ns
Notes
1.
C
PD
is used to determine the dynamic power dissipation (P
D
in
μ
W):
P
D
= C
PD
×
V
CC2
×
f
i
+ ∑
(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz
f
o
= output frequency in MHz
∑
(C
L
×
V
CC2
×
f
o
) = sum of outputs
C
L
= output load capacitance in pF
V
CC
= supply voltage in V
For HC the condition is V
I
= GND to V
CC
For HCT the condition is V
I
= GND to V
CC
1.5 V.
2.
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information”
.
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
HC
HCT
t
PHL
/ t
PLH
propagation delay
nCP to nQ, nQ
nS
D
to nQ, nQ
nR
D
to nQ, nQ
maximum clock frequency
input capacitance
power dissipation
capacitance per flip-flop
C
L
= 15 pF;
V
CC
= 5 V
15
12
12
75
3.5
20
17
14
15
61
3.5
22
ns
ns
ns
MHz
pF
pF
f
max
C
I
C
PD
notes 1 and 2
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