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參數(shù)資料
| 型號： | 74F2373 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Octal transparent latch with 30Ωequivalent output termination (3-State)(帶30Ω等值輸出終端電阻的八透明鎖存器（三態(tài)）) |
| 中文描述： | 八路透明鎖存30Ωequivalent輸出端接（3態(tài)）（帶30Ω等值輸出終端電阻的八透明鎖存器（三態(tài)）） |
| 文件頁數(shù)： | 2/10頁 |
| 文件大?。?/td> | 84K |
| 代理商： | 74F2373 |
Philips Semiconductors
Product specification
74F2373
Octal transparent latch with 30
equivalent output
termination (3-State)
2
1999 Feb 01
853-2140 20747
FEATURES
8-bit transparent latch
30 Ohm output termination for driving DRAM
3-State outputs glitch free during power-up and power-down
Common 3-State output register
Independent register and 3-State buffer operation
DESCRIPTION
The 74F2373 is an octal transparent latch coupled to eight 3-State
output devices. The two sections of the device are controlled
independently by enable (E) and output enable (OE) control gates.
The 30 Ohm series termination on the outputs reduces
over/undershoot, making them ideal for driving DRAM
The data on the D inputs is transferred to the latch outputs when the
enable (E) input is high. The latch remains transparent to the data
input while E is high, and stores the data that is present one setup
time before the high-to-low enable transition.
The 3-State output buffers are designed to drive heavily loaded
3-State buses, MOS memories, or MOS microprocessors.
The active low output enable (OE) controls all eight 3-State buffers
independent of the latch operation. When OE is low, latched or
transparent data appears at the output.
When OE is high, the outputs are in high impedance “off” state,
which means they will neither drive nor load the bus.
TYPE
TYPICAL
PROPAGATION
DELAY
TYPICAL SUPPLY
CURRENT
(TOTAL)
74F2373
4.5ns
35mA
ORDERING INFORMATION
ORDER CODE
DESCRIPTION
COMMERCIAL RANGE
V
CC
= 5V
±
10%, T
amb
= 0
°
C to +70
°
C
DRAWING NUMBER
20-pin plastic DIP
N74F2373N
SOT146-1
20-pin plastic SOL
N74F2373D
SOT163-1
INPUT AND OUTPUT LOADING AND FAN OUT TABLE
PINS
DESCRIPTION
74F (U.L.)
HIGH/LOW
LOAD VALUE
HIGH/LOW
D0 - D7
Data inputs
1.0/1.0
20
μ
A
/
0.6mA
E
Enable input (active high)
1.0/1.0
20
μ
A/0.6mA
OE
Output enable inputs (active low)
1.0/1.0
20
μ
A/0.6mA
Q0 - Q7
3-State outputs
150/40
3.0mA/3.0mA
NOTE:
One (1.0) FAST unit load is defined as: 20
μ
A in the high state and 0.6mA in the low state.
PIN CONFIGURATION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
OE
Q0
D0
D1
Q1
Q2
D2
D3
Q3
GND
V
CC
Q7
D7
D6
Q6
Q5
D5
D4
Q4
E
SF00250
LOGIC SYMBOL
E
OE
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
D0 D1 D2 D3 D4 D5 D6 D7
3
4
7
8
13
14
17
18
2
5
6
9
12
15
16
19
V
= Pin 20
GND = Pin 10
11
1
SF00251
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