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參數(shù)資料
| 型號(hào)： | 74ALVCH16652 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | 16-bit transceiver/register with dual enable; 3-state |
| 中文描述： | 16位收發(fā)器/寄存器雙使，三態(tài) |
| 文件頁(yè)數(shù)： | 2/20頁(yè) |
| 文件大?。?/td> | 103K |
| 代理商： | 74ALVCH16652 |
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1999 Nov 23
2
Philips Semiconductors
Product specification
16-bit transceiver/register with dual enable; 3-state
74ALVCH16652
FEATURES
In accordance with JEDEC standard no. 8-1A
CMOS low power consumption
MULTIBYTE
flow-through pin-out architecture
Low inductance, multiple supply and ground pins for
minimum noise and ground bounce
Direct interface with TTL levels
All data inputs have bus hold
Output drive capability 50
transmission lines at 85
°
C
Current drive
±
24 mA at 3.0 V.
DESCRIPTION
The 74ALVCH16652 consists of 16 non-inverting bus
transceiver circuits with 3-state outputs, D-type flip-flops
and control circuitry arranged for multiplexed transmission
of data directly from the data bus or from the internal
storage registers.
Data on the ‘A’ or ‘B’, or both buses, will be stored in the
internal registers, at the appropriate clock inputs
(nCP
AB
or nCP
BA
) regardless of the select inputs (nS
AB
and nS
BA
) or output enable (nOE
AB
and nOE
BA
) control
inputs.
Depending on the select inputs nS
AB
and nS
BA
data can
directly go from input to output (real-time mode) or data
can be controlled by the clock (storage mode), when OE
inputs permit this operating mode.
The output enable inputs nOE
AB
and nOE
BA
determine the
operation mode of the transceiver. When nOE
AB
is LOW,
no data transmission from nB
n
to nA
n
is possible and when
nOE
BA
is HIGH, no data transmission from nB
n
to nA
n
is
possible.
When nS
AB
and nS
BA
are in the real-time transfer mode, it
is also possible to store data without using the internal
D-type flip-flops by simultaneously enabling nOE
AB
and
nOE
BA
. In this configuration each output reinforces its
input.
Active bus hold circuitry is provided to hold unused or
floating data inputs at a valid logic level.
QUICK REFERENCE DATA
Ground = 0; T
amb
= 25
°
C; t
r
= t
f
= 2.5 ns.
Notes
1.
C
PD
is used to determine the dynamic power dissipation (P
D
in
μ
W).
P
D
= C
PD
×
V
CC2
×
f
i
+
Σ
(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz;
C
L
= output load capacitance in pF;
f
o
= output frequency in MHz;
V
CC
= supply voltage in Volts;
Σ
(C
L
×
V
CC2
×
f
o
) = sum of outputs.
The condition is V
I
= GND to V
CC
.
2.
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
t
PHL
/t
PLH
f
max
C
I
C
PD
propagation delay nA
n
, nB
n
to nB
n
, nA
n
maximum clock frequency
input capacitance
power dissipation capacitance per latch
C
L
= 50 pF; V
CC
= 3.3 V
2.6
350
4.0
ns
MHz
pF
notes 1 and 2
outputs enabled
outputs disabled
22
4.0
pF
pF
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 74ALVCH16652DG | 功能描述:總線收發(fā)器 16-BIT SCVR/REG 3-S RoHS:否 制造商:Fairchild Semiconductor 邏輯類(lèi)型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類(lèi)型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時(shí)間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| 74ALVCH16652DGG | 制造商:PHILIPS 制造商全稱(chēng):NXP Semiconductors 功能描述:16-bit transceiver/register with dual enable; 3-state |
| 74ALVCH16652DGG,11 | 功能描述:總線收發(fā)器 16-BIT SCVR/REG 3-S RoHS:否 制造商:Fairchild Semiconductor 邏輯類(lèi)型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類(lèi)型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時(shí)間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| 74ALVCH16652DGG,112 | 制造商:NXP Semiconductors 功能描述: |
| 74ALVCH16652DGG,118 | 制造商:NXP Semiconductors 功能描述: |
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