參數(shù)資料
型號(hào): 74ALVCH16652
廠商: NXP Semiconductors N.V.
英文描述: 16-bit transceiver/register with dual enable; 3-state
中文描述: 16位收發(fā)器/寄存器雙使,三態(tài)
文件頁數(shù): 14/20頁
文件大?。?/td> 103K
代理商: 74ALVCH16652
1999 Nov 23
14
Philips Semiconductors
Product specification
16-bit transceiver/register with dual enable; 3-state
74ALVCH16652
Fig.10 Load circuitry for switching times.
V
CC
V
I
<2.7 V
2.7 to 3.6 V 2.7 V
V
CC
TEST
S1
t
PLH
/t
PHL
t
PLZ
/t
PZL
t
PHZ
/t
PZH
open
2
×
V
CC
GND
handbook, full pagewidth
open
GND
50 pF
2
×
VCC
VCC
VI
VO
MNA296
D.U.T.
CL
RT
RL
500
RL
500
PULSE
GENERATOR
S1
Definitions for test circuit.
C
= load capacitance including jig and probe capacitance
(See Chapter “AC characteristics”).
R
L
= load resistance.
R
= termination resistance should be equal to the output impedance Z
o
of the pulse generator.
APPLICATION INFORMATION
Fig.11 Real-time transfer; bus B to bus A.
handbook, halfpage
MNA325
B
B
L
L
CPAB
X
CPBA
X
SAB
X
SBA
L
OEAB
OEBA
Fig.12 Real-time transfer; bus A to bus B.
handbook, halfpage
MNA326
B
B
H
H
CPAB
X
CPBA
X
SAB
L
SBA
X
OEAB
OEBA
相關(guān)PDF資料
PDF描述
74ALVCH16821 Quadruple Positive-NAND Gates With Schmitt-Trigger Inputs 14-TSSOP -40 to 85
74ALVCH16823 Automotive Catalog Quadruple Positive-NAND Gates With Schmitt-Trigger Inputs 14-SOIC -40 to 125
74ALVCH16825 Automotive Catalog Quadruple Positive-NAND Gates With Schmitt-Trigger Inputs 14-TSSOP -40 to 125
74ALVCH16827 20-bit buffer/line driver, non-inverting 3-State
74ALVCH16841DL 20-bit bus interface D-type latch (3-State)
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74ALVCH16652DGG,112 制造商:NXP Semiconductors 功能描述:
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