參數(shù)資料
型號(hào)： 74ALVCH16652
廠商： NXP Semiconductors N.V.
英文描述： 16-bit transceiver/register with dual enable; 3-state
中文描述： 16位收發(fā)器/寄存器雙使，三態(tài)
文件頁(yè)數(shù)： 11/20頁(yè)
文件大?。?/td> 103K
代理商： 74ALVCH16652
1999 Nov 23
11
Philips Semiconductors
Product specification
16-bit transceiver/register with dual enable; 3-state
74ALVCH16652
AC CHARACTERISTICS FOR V
CC
= 2.7 V AND V
CC
= 3.0 TO 3.6 V
Ground = 0 V; t
r
= t
f
≤
2.5 ns; C
L
= 50 pF.
Notes
1.
2.
All typical values are measured at T
amb
= 25
°
C.
Typical values at V
CC
= 3.3 V.
SYMBOL
PARAMETER
TEST CONDITIONS
T
amb
=
40 TO +85
°
C
UNIT
WAVEFORMS
V
CC
(V)
2.7
3.0 to 3.6
2.7
3.0 to 3.6
2.7
3.0 to 3.6
2.7
3.0 to 3.6
2.7
3.0 to 3.6
2.7
3.0 to 3.6
2.7
3.0 to 3.6
2.7
3.0 to 3.6
2.7
3.0 to 3.6
2.7
3.0 to 3.6
2.7
3.0 to 3.6
MIN.
TYP.
(1)
MAX.
t
PHL
/t
PLH
propagation delay
nA
n
, nB
n
to nB
n
, nA
n
see Figs 6 and 10
1.0
1.4
1.3
1.0
1.4
1.0
1.1
3.3
3.3
1.7
1.4
0.4
0.7
150
150
2.8
2.6
(2)
3.1
2.9
(2)
3.5
3.1
(2)
2.4
2.2
(2)
3.4
2.7
(2)
3.0
2.2
(2)
3.1
2.9
(2)
1.0
0.7
(2)
0.2
0.3
(2)
0.1
0.2
(2)
320
320
(2)
4.5
3.9
5.2
4.5
6.4
5.3
4.6
4.0
5.1
4.5
4.6
4.0
5.1
4.5
ns
propagation delay
nCP
AB
, nCP
BA
to nB
n
, nA
n
see Figs 8 and 10
ns
propagation delay
nS
AB
, nS
BA
to nB
n
, nA
n
see Figs 7 and 10
ns
t
PZH
/t
PZL
3-state output enable time
nOE
AB
to nB
n
see Figs 9 and 10
ns
t
PHZ
/t
PLZ
3-state output disable time
nOE
AB
to nB
n
see Figs 9 and 10
ns
t
PZH
/t
PZL
3-state output enable time
nOE
BA
to nA
n
see Figs 9 and 10
ns
t
PHZ
/t
PLZ
3-state output disable time
nOE
BA
to nA
n
see Figs 9 and 10
ns
t
W
clock pulse width HIGH or
LOW nCP
AB
or nCP
BA
see Figs 8 and 10
ns
t
su
set-up time
nA
n
, nB
n
to nCP
AB
, nCP
BA
see Figs 8 and 10
ns
t
h
hold time
nA
n
, nB
n
to nCP
AB
, nCP
BA
see Figs 8 and 10
ns
f
max
maximum clock pulse
frequency
see Figs 8 and 10
MHz
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