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參數(shù)資料
| 型號： | 74ACT715 |
| 廠商： | Fairchild Semiconductor Corporation |
| 英文描述： | 8-Bit LVTTL-GTLP Adjustable-Edge-Rate Registered Transceiver with Split LVTTL Port and Feedback Path 48-TSSOP -40 to 85 |
| 中文描述： | 可編程視頻同步發(fā)生器 |
| 文件頁數(shù)： | 4/14頁 |
| 文件大?。?/td> | 127K |
| 代理商： | 74ACT715 |
www.fairchildsemi.com
4
7
Signal Specification
HORIZONTAL SYNC AND BLANK
SPECIFICATIONS
All horizontal signals are defined by a start and end time.
The start and end times are specified in number of clock
cycles per line. The start of the horizontal line is considered
pulse 1 not 0. All values of the horizontal timing registers
are referenced to the falling edge of the Horizontal Blank
signal (see Figure 1). Since the first CLOCK edge, CLOCK
#1, causes the first falling edge of the Horizontal Blank ref-
erence pulse, edges referenced to this first Horizontal edge
are n
+
1 CLOCKs away, where “n” is the width of the tim-
ing in question. Registers 1, 2, and 3 are programmed in
this manner. The horizontal counters start at 1 and count
until HMAX. The value of HMAX must be divisible by 2.
This limitation is imposed because during interlace opera-
tion this value is internally divided by 2 in order to generate
serration and equalization pulses at 2
×
the horizontal fre-
quency. Horizontal signals will change on the falling edge
of the CLOCK signal. Signal specifications are shown
below.
FIGURE 1. Horizontal Waveform Specification
=
REG(4)
×
ckper
=
[REG(3)
1]
×
ckper
=
[REG(2)
REG(1)]
×
ckper
=
[REG(1)
1]
×
ckper
Horizontal Period (HPER)
Horizontal Blanking Width:
Horizontal Sync Width:
Horizontal Front Porch:
VERTICAL SYNC AND BLANK SPECIFICATION
All vertical signals are defined in terms of number of lines
per frame. This is true in both interlaced and noninterlaced
modes of operation. Care must be taken to not specify the
Vertical Registers in terms of lines per field. Since the first
CLOCK edge, CLOCK #1, causes the first falling edge of
the Vertical Blank (first Horizontal Blank) reference pulse,
edges referenced to this first edge are n
+
1 lines away,
where “n” is the width of the timing in question. Registers 5,
6, and 7 are programmed in this manner. Also, in the inter-
laced mode, vertical timing is based on half-lines. There-
fore registers 5, 6, and 7 must contain a value twice the
total horizontal (odd and even) plus 1 (as described
above). In non-interlaced mode, all vertical timing is based
on whole-lines. Register 8 is always based on whole-lines
and does not add 1 for the first clock. The vertical counter
starts at the value of 1 and counts until the value of VMAX.
No restrictions exist on the values placed in the vertical
registers. Vertical Blank will change on the leading edge of
HBLANK. Vertical Sync will change on the leading edge of
HSYNC. (See Figure 2.) Vertical Frame Period (VPER)
=
REG(8)
×
hper
Vertical Field Period (VPER/n)
=
REG(8)
×
hper/n
Vertical Blanking Width
=
[REG(7)
1]
×
hper/n
Vertical Syncing Width
=
[REG(6)
REG(5)]
×
hper/n
Vertical Front Porch
=
[REG(5)
1]
×
hper/n
where
n
=
1 for noninterlaced
n
=
2 for interlaced
COMPOSITE SYNC AND BLANK SPECIFICATION
Composite Sync and Blank signals are created by logically
ANDing (ORing) the active LOW (HIGH) signals of the cor-
responding vertical and horizontal components of these
signals. The Composite Sync signal may also include ser-
ration and/or equalization pulses. The Serration pulse inter-
val occurs in place of the Vertical Sync interval.
Equalization pulses occur preceding and/or following the
Serration pulses. The width and location of these pulses
can be programmed through the registers shown below.
(See Figure 3.)
Horizontal Equalization PW
=
[REG(9)
REG(1)]
×
ckper
REG 9
=
(HFP)
+
(HEQP)
+
1
Horizontal Serration PW:
=
[REG(4)/n
REG(10)]
×
ckper
REG 10
=
(HFP)
+
(HPER/2)
(HSERR)
+
1
Where
n
=
1 for noninterlaced single serration/equal-
ization
n
=
2 for noninterlaced double serration/equal-
ization
n
=
2 for interlaced operation
+
REG(1)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 74ACT715-RPC | Programmable Video Sync Generator |
| 74ACT715-RSC | 8-Bit LVTTL-GTLP Adjustable-Edge-Rate Registered Transceiver with Split LVTTL Port and Feedback Path 48-TVSOP -40 to 85 |
| 74ACT715PC | Programmable Video Sync Generator |
| 74ACT715SC | 8-Bit LVTTL-GTLP Adjustable-Edge-Rate Registered Transceiver with Split LVTTL Port and Feedback Path 48-TSSOP -40 to 85 |
| 74ACT715-R | Programmable Video Sync Generator |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 74ACT715PC | 功能描述:視頻 IC Prog Vid Sync Gen RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel |
| 74ACT715PC_Q | 功能描述:視頻 IC Prog Vid Sync Gen RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel |
| 74ACT715RPC | 功能描述:視頻 IC Prog Vid Sync Gen RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel |
| 74ACT715RSC | 功能描述:視頻 IC Prog Vid Sync Gen RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel |
| 74ACT715-RSC | 功能描述:IC GEN PROG VIDEO SYNC 20-SOIC RoHS:是 類別:集成電路 (IC) >> 線性 - 視頻處理 系列:- 產(chǎn)品變化通告:Product Discontinuation 07/Mar/2011 標(biāo)準(zhǔn)包裝:3,000 系列:OMNITUNE™ 類型:調(diào)諧器 應(yīng)用:移動電話，手機，視頻顯示器 安裝類型:表面貼裝 封裝/外殼:65-WFBGA 供應(yīng)商設(shè)備封裝:PG-WFSGA-65 包裝:帶卷 (TR) 其它名稱:SP000365064 |
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