參數(shù)資料
型號： 73S1210F-68M/F/PG
廠商： Maxim Integrated
文件頁數(shù)： 59/126頁
文件大小： 0K
描述： IC SOC SMART CARD READER 68QFN
標(biāo)準(zhǔn)包裝： 260
系列： *
73S1210F Data Sheet
DS_1210F_001
38
Rev. 1.4
Table 26: Control Bits for External Interrupts
Enable Bit
Description
Flag Bit
Description
EX0
Enable external interrupt 0
IE0
External interrupt 0 flag
EX1
Enable external interrupt 1
IE1
External interrupt 1 flag
EX2
Enable external interrupt 2
IEX2
External interrupt 2 flag
EX3
Enable external interrupt 3
IEX3
External interrupt 3 flag
EX4
Enable external interrupt 4
IEX4
External interrupt 4 flag
EX5
Enable external interrupt 5
IEX5
External interrupt 5 flag
EX6
Enable external interrupt 6
IEX6
External interrupt 6 flag
1.7.5.4
Power Down Interrupt Logic
The 73S1210F contains special interrupt logic to allow INT0 to wake up the CPU from a power down
(CPU STOP) state. See the Power Control Modes section for details.
1.7.5.5
Interrupt Priority Level Structure
All interrupt sources are combined in groups, as shown in Table 27.
Table 27: Priority Level Groups
Group
0
External interrupt 0
Serial channel 1 interrupt
1
Timer 0 interrupt
–
External interrupt 2
2
External interrupt 1
–
External interrupt 3
3
Timer 1 interrupt
–
External interrupt 4
4
Serial channel 0 interrupt
–
External interrupt 5
5
–
External interrupt 6
Each group of interrupt sources can be programmed individually to one of four priority levels by setting or
clearing one bit in the special function register IP0 and one in IP1. If requests of the same priority level
are received simultaneously, an internal polling sequence as per Table 31 determines which request is
serviced first.
IEN enable bits must be set to permit any of these interrupts to occur. Likewise, each interrupt has its
own flag bit that is set by the interrupt hardware and is reset automatically by the MPU interrupt handler.
Interrupt Priority 0 Register (IP0): 0xA9
0x00
Table 28: The IP0 Register
MSB
LSB
–
WDTS
IP0.5
IP0.4
IP0.3
IP0.2
IP0.1
IP0.0
Note: WDTS is not used for interrupt controls.
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73S1210F-68MR/F/PJ 功能描述:80515 73S12xx Microcontroller IC 8-Bit 24MHz 32KB (32K x 8) FLASH 68-QFN (8x8) 制造商:maxim integrated 系列:73S12xx 包裝:帶卷（TR） 零件狀態(tài):要求報價 核心處理器:80515 核心尺寸:8-位 速度:24MHz 連接性:I2C，智能卡，UART/USART 外設(shè):LED，POR，WDT I/O 數(shù):8 程序存儲容量:32KB（32K x 8） 程序存儲器類型:閃存 EEPROM 容量:- RAM 容量:2K x 8 電壓 - 電源（Vcc/Vdd）:2.7 V ~ 6.5 V 數(shù)據(jù)轉(zhuǎn)換器:- 振蕩器類型:內(nèi)部 工作溫度:-40°C ~ 85°C（TA） 封裝/外殼:68-VFQFN 裸露焊盤 供應(yīng)商器件封裝:68-QFN（8x8） 標(biāo)準(zhǔn)包裝:2,500
73S1210F-EB 功能描述:開發(fā)板和工具包 - 8051 73S1210F Eval Brd (Doc. Cd, Cable) RoHS:否 制造商:Silicon Labs 產(chǎn)品:Development Kits 工具用于評估:C8051F960, Si7005 核心: 接口類型:USB 工作電源電壓:
73S1210F-EB-Lite 功能描述:開發(fā)板和工具包 - 8051 73S1210F Eval Brd Lite w/Doc Cd, Cable RoHS:否 制造商:Silicon Labs 產(chǎn)品:Development Kits 工具用于評估:C8051F960, Si7005 核心: 接口類型:USB 工作電源電壓:
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