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參數(shù)資料
| 型號： | 70V657S12BFG8 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | SRAM |
| 英文描述： | 32K X 36 DUAL-PORT SRAM, 12 ns, PBGA208 |
| 封裝： | 15 X 15 MM, 1.40 MM HEIGHT, 0.80 MM PITCH, FPBGA-208 |
| 文件頁數(shù)： | 1/24頁 |
| 文件大小： | 316K |
| 代理商： | 70V657S12BFG8 |
2004 Integrated Device Technology, Inc.
1
MARCH 2004
DSC-4869/5
CE0R
R/
WR
CE1R
BE0R
BE1R
BE2R
BE3R
128/64/32K x 36
MEMORY
ARRAY
Address
Decoder
A16R(1)
A0R
Address
Decoder
CE0L
R/
WL
CE1L
BE0L
BE1L
BE2L
BE3L
Dout0-8_L
Dout9-17_L
Dout18-26_L
Dout27-35_L
Dout0-8_R
Dout9-17_R
Dout18-26_R
Dout27-35_R
B
E
0
L
B
E
1
L
B
E
2
L
B
E
3
L
B
E
3
R
B
E
2
R
B
E
1
R
B
E
0
R
I/O0L- I/O35L
A16 L(1)
A0L
I/O0R -I/O35R
Di n_L
ADDR_L
Di n_R
ADDR_R
OER
OEL
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
SEML
INTL(3)
BUSYL(2,3)
M/
S
R/
WL
OEL
R/
WR
OER
CE0L
CE1L
CE0R
CE1R
BUSYR(2,3)
SEMR
INTR(3)
TMS
TCK
TRST
TDI
TDO
JTAG
4869 drw 01
Functional Block Diagram
◆
Full on-chip hardware support of semaphore signaling
between ports
◆
Fully asynchronous operation from either port
◆
Separate byte controls for multiplexed bus and bus
matching compatibility
◆
Supports JTAG features compliant to IEEE 1149.1
◆
LVTTL-compatible, single 3.3V (±150mV) power supply for
core
◆
LVTTL-compatible, selectable 3.3V (±150mV)/2.5V (±100mV)
power supply for I/Os and control signals on each port
◆
Available in a 208-pin Plastic Quad Flatpack, 208-ball fine
pitch Ball Grid Array, and 256-ball Ball Grid Array
◆
Industrial temperature range (–40°C to +85°C) is available
for selected speeds
Features
◆
True Dual-Port memory cells which allow simultaneous
access of the same memory location
◆
High-speed access
– Commercial: 10/12/15ns (max.)
– Industrial: 12/15ns (max.)
◆
Dual chip enables allow for depth expansion without
external logic
◆
IDT70V659/58/57 easily expands data bus width to 72 bits
or more using the Master/Slave select when cascading
more than one device
◆
M/S = VIH for BUSY output flag on Master,
M/S = VIL for BUSY input on Slave
◆
Busy and Interrupt Flags
◆
On-chip port arbitration logic
HIGH-SPEED 3.3V
128/64/32K x 36
ASYNCHRONOUS DUAL-PORT
STATIC RAM
IDT70V659/58/57S
1. A16 is a NC for IDT70V658. Also, Addresses A16 and A15 are NC's for IDT70V657.
2. BUSY is an input as a Slave (M/S=VIL) and an output when it is a Master (M/S=VIH).
3. BUSY and INT are non-tri-state totem-pole outputs (push-pull).
NOTES:
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 70V657S12BFGI | 功能描述:靜態(tài)隨機存取存儲器 32Kx36 STD-PWR, 3.3V DUAL-PORT RAM RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| 70V657S12BFGI8 | 制造商:Integrated Device Technology Inc 功能描述:SRAM Chip Async Dual 3.3V 1.125M-Bit 32K x 36 12ns 208-Pin CABGA T/R 制造商:Integrated Device Technology Inc 功能描述:SRAM ASYNC DUAL 3.3V 1.125MBIT 32KX36 12NS 208FPBGA - Tape and Reel 制造商:Integrated Device Technology Inc 功能描述:32Kx36 STD-PWR, 3.3V DUAL-PORT RAM |
| 70V657S12BFI | 功能描述:靜態(tài)隨機存取存儲器 32Kx36 STD-PWR, 3.3V DUAL-PORT RAM RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| 70V657S12BFI8 | 制造商:Integrated Device Technology Inc 功能描述:SRAM Chip Async Dual 3.3V 1.125M-Bit 32K x 36 12ns 208-Pin CABGA T/R 制造商:Integrated Device Technology Inc 功能描述:SRAM ASYNC DUAL 3.3V 1.125MBIT 32KX36 12NS 208CABGA - Tape and Reel 制造商:Integrated Device Technology Inc 功能描述:32Kx36 STD-PWR, 3.3V DUAL-PORT RAM |
| 70V657S12DR | 功能描述:靜態(tài)隨機存取存儲器 32Kx36 STD-PWR, 3.3V DUAL-PORT RAM RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
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