參數(shù)資料
型號： 70V657S12BFG8
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： SRAM
英文描述： 32K X 36 DUAL-PORT SRAM, 12 ns, PBGA208
封裝： 15 X 15 MM, 1.40 MM HEIGHT, 0.80 MM PITCH, FPBGA-208
文件頁數(shù)： 7/24頁
文件大?。?/td> 316K
代理商： 70V657S12BFG8
15
IDT70V659/58/57S
High-Speed 3.3V 128/64/32K x 36 Asynchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
NOTES:
1. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveform of Write with Port-to-Port Read and BUSY (M/S = VIH)".
2. To ensure that the earlier of the two ports wins.
3. tBDD is a calculated parameter and is the greater of the Max. spec, tWDD – tWP (actual), or tDDD – tDW (actual).
4. To ensure that the write cycle is inhibited on port "B" during contention on port "A".
5. To ensure that a write cycle is completed on port "B" after contention on port "A".
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range
Symbol
Parameter
70V659/58/57S10
Com'l Only
70V659/58/57S12
Com'l
& Ind
70V659/58/57S15
Com'l
& Ind
Unit
Min.
Max.
Min.
Max.
Min.
Max.
BUSY
TIMING (M/S=VIH)
tBAA
BUSY
Access Time from Address Match
____
10
____
12
____
15
ns
tBDA
BUSY
Disable Time from Address Not Matched
____
10
____
12
____
15
ns
tBAC
BUSY
Access Time from Chip Enable Low
____
10
____
12
____
15
ns
tBDC
BUSY
Disable Time from Chip Enable High
____
10
____
12
____
15
ns
tAPS
Arbitration Priority Set-up Time(2)
5
____
5
____
5
____
ns
tBDD
BUSY
Disable to Valid Data(3)
____
10
____
12
____
15
ns
tWH
Write Hold After BUSY(5)
8
____
10
____
12
____
ns
BUSY
TIMING (M/S=VIL)
tWB
BUSY
Input to Write(4)
0
____
0
____
0
____
ns
tWH
Write Hold After BUSY(5)
8
____
10
____
12
____
ns
PORT-TO-PORT DELAY TIMING
tWDD
Write Pulse to Data Delay(1)
____
22
____
25
____
30
ns
tDDD
Write Data Valid to Read Data Delay(1)
____
20
____
22
____
25
ns
4869 tbl 14
相關(guān)PDF資料
PDF描述
71-570125-8P 8 CONTACT(S), ALUMINUM, CADMIUM PLATED, MALE, MIL SERIES CONNECTOR, SOLDER, RECEPTACLE
71-570125-8S 8 CONTACT(S), ALUMINUM, CADMIUM PLATED, FEMALE, MIL SERIES CONNECTOR, SOLDER, RECEPTACLE
71-570125-99P 23 CONTACT(S), ALUMINUM, CADMIUM PLATED, MALE, MIL SERIES CONNECTOR, SOLDER, RECEPTACLE
71-570125-99S 23 CONTACT(S), ALUMINUM, CADMIUM PLATED, FEMALE, MIL SERIES CONNECTOR, SOLDER, RECEPTACLE
71-570126-11P 11 CONTACT(S), ALUMINUM, CADMIUM PLATED, MALE, MIL SERIES CONNECTOR, SOLDER, RECEPTACLE
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
70V657S12BFGI 功能描述:靜態(tài)隨機(jī)存取存儲器 32Kx36 STD-PWR, 3.3V DUAL-PORT RAM RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray
70V657S12BFGI8 制造商:Integrated Device Technology Inc 功能描述:SRAM Chip Async Dual 3.3V 1.125M-Bit 32K x 36 12ns 208-Pin CABGA T/R 制造商:Integrated Device Technology Inc 功能描述:SRAM ASYNC DUAL 3.3V 1.125MBIT 32KX36 12NS 208FPBGA - Tape and Reel 制造商:Integrated Device Technology Inc 功能描述:32Kx36 STD-PWR, 3.3V DUAL-PORT RAM
70V657S12BFI 功能描述:靜態(tài)隨機(jī)存取存儲器 32Kx36 STD-PWR, 3.3V DUAL-PORT RAM RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray
70V657S12BFI8 制造商:Integrated Device Technology Inc 功能描述:SRAM Chip Async Dual 3.3V 1.125M-Bit 32K x 36 12ns 208-Pin CABGA T/R 制造商:Integrated Device Technology Inc 功能描述:SRAM ASYNC DUAL 3.3V 1.125MBIT 32KX36 12NS 208CABGA - Tape and Reel 制造商:Integrated Device Technology Inc 功能描述:32Kx36 STD-PWR, 3.3V DUAL-PORT RAM
70V657S12DR 功能描述:靜態(tài)隨機(jī)存取存儲器 32Kx36 STD-PWR, 3.3V DUAL-PORT RAM RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*