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| 型號： | 68HC705PL4B |
| 廠商： | Motorola, Inc. |
| 英文描述： | 8-Bit Microcontroller Units (MCU).(8位微控制器) |
| 中文描述： | 8位微控制器單元（MCU）。（8位微控制器） |
| 文件頁數(shù)： | 53/98頁 |
| 文件大小： | 1019K |
| 代理商： | 68HC705PL4B |
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April 30, 1998
GENERAL RELEASE SPECIFICATION
MC68HC05PL4
REV 2.0
16-BIT PROGRAMMABLE TIMER
MOTOROLA
9-3
The timer registers (TMRH, TMRL) shown in
Figure 9-3
are read-only locations
which contain the current high and low bytes of the 16-bit free-running counter.
Writing to the timer registers has no effect. Reset of the device presets the timer
counter to $FFFC.
The TMRL latch is a transparent read of the LSB until the a read of the TMRH
takes place. A read of the TMRH latches the LSB into the TMRL location until the
TMRL is again read. The latched value remains fixed even if multiple reads of the
TMRH take place before the next read of the TMRL. Therefore, when reading the
MSB of the timer at TMRH the LSB of the timer at TMRL must also be read to
complete the read sequence.
During power-on-reset (POR), the counter is initialized to $FFFC and begins
counting after the oscillator start-up delay. Because the counter is sixteen bits and
preceded by a fixed divide-by-four prescaler, the value in the counter repeats
every 262, 144 internal bus clock cycles (524, 288 oscillator cycles).
When the free-running counter rolls over from $FFFF to $0000, the timer overflow
flag bit (TOF) is set in the TSR. When the TOF is set, it can generate an interrupt if
the timer overflow interrupt enable bit (TOIE) is also set in the TCR. The TOF flag
bit can only be reset by reading the TMRL after reading the TSR.
Other than clearing any possible TOF flags, reading the TMRH and TMRL in any
order or any number of times does not have any effect on the 16-bit free-running
counter.
NOTE
To prevent interrupts from occurring between readings of the TMRH and TMRL,
set the I bit in the condition code register (CCR) before reading TMRH and clear
the I bit after reading TMRL.
BIT 7
BIT 6
TMRH6
BIT 5
TMRH5
BIT 4
TMRH4
BIT 3
TMRH3
BIT 2
TMRH2
BIT 1
TMRH1
BIT 0
TMRH0
TMRH
$0018
R TMRH7
W
reset:
1
1
1
1
1
1
1
1
TMRL
$0019
R TMRL7
W
TMRL6
TMRL5
TMRL4
TMRL3
TMRL2
TMRL1
TMRL0
reset:
1
1
1
1
1
1
0
0
Figure 9-3. Programmable Timer Registers (TMRH, TMRL)
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