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| 型號(hào)： | 68HC05J5A |
| 廠商： | Motorola, Inc. |
| 英文描述： | 8-Bit Microcontroller Units (MCU).(8位微控制器) |
| 中文描述： | 8位微控制器單元（MCU）。（8位微控制器） |
| 文件頁(yè)數(shù)： | 81/106頁(yè) |
| 文件大小： | 1069K |
| 代理商： | 68HC05J5A |
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July 16, 1999
GENERAL RELEASE SPECIFICATION
MC68HC05J5A
REV 2.1
INSTRUCTION SET
MOTOROLA
10-13
SUB #opr
SUB opr
SUB opr
SUB oprX
SUB oprX
SUB ,X
Subtract Memory
Byte from
Accumulator
A
←
(A) – (M)
— —
¤
¤
¤
IMM
DIR
EXT
IX2
IX1
IX
A0
B0
C0
D0
E0
F0
ii
dd
hh ll
ee ff
ff
2
3
4
5
4
3
SWI
Software Interrupt
PC
←
(PC) + 1; Push (PCL)
SP
←
(SP) – 1; Push (PCH)
SP
←
(SP) – 1; Push (X)
SP
←
(SP) – 1; Push (A)
SP
←
(SP) – 1; Push (CCR)
SP
←
(SP) – 1; I
←
1
PCH
←
Interrupt Vector High Byte
PCL
←
Interrupt Vector Low Byte
— 1 — — —
INH
83
10
TAX
Transfer
Accumulator to
Index Register
X
←
(A)
— — — — —
INH
97
2
TST opr
TSTA
TSTX
TST oprX
TST ,X
Test Memory Byte
for Negative or Zero
(M) – $00
— —
¤
¤
—
DIR
INH
INH
IX1
IX
3D
4D
5D
6D
7D
dd
ff
4
3
3
5
4
TXA
Transfer Index
Register to
Accumulator
Stop CPU Clock and
Enable
Interrupts
A
←
(X)
— — — — —
INH
9F
2
WAIT
— 0 — — —
INH
8F
2
A
C
CCR
dd
dd rr
DIR
ee ff
EXT
ff
H
hh ll
I
ii
IMM
INH
IX
IX1
IX2
M
N
n
Accumulator
Carry/borrow flag
Condition code register
Direct address of operand
Direct address of operand and relative offset of branch instruction
Direct addressing mode
High and low bytes of offset in indexed, 16-bit offset addressing
Extended addressing mode
Offset byte in indexed, 8-bit offset addressing
Half-carry flag
High and low bytes of operand address in extended addressing
Interrupt mask
Immediate operand byte
Immediate addressing mode
Inherent addressing mode
Indexed, no offset addressing mode
Indexed, 8-bit offset addressing mode
Indexed, 16-bit offset addressing mode
Memory location
Negative flag
Any bit
opr
PC
PCH
PCL
REL
rel
rr
SP
X
Z
#
∧
∨
⊕
( )
–( )
←
:
¤
—
Operand (one or two bytes)
Program counter
Program counter high byte
Program counter low byte
Relative addressing mode
Relative program counter offset byte
Relative program counter offset byte
Stack pointer
Index register
Zero flag
Immediate value
Logical AND
Logical OR
Logical EXCLUSIVE OR
Contents of
Negation (two’s complement)
Loaded with
If
Concatenated with
Set or cleared
Not affected
Table 10-6. Instruction Set Summary (Continued)
Source
Form
Operation
Description
Effect on
CCR
A
M
O
O
C
H I N Z C
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