- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄369230 > 68HC05BD7 (Motorola, Inc.) 8-Bit Microcontroller Units (MCU).(8位微控制器) PDF資料下載
參數(shù)資料
| 型號： | 68HC05BD7 |
| 廠商： | Motorola, Inc. |
| 英文描述： | 8-Bit Microcontroller Units (MCU).(8位微控制器) |
| 中文描述： | 8位微控制器單元（MCU）。（8位微控制器） |
| 文件頁數(shù)： | 61/85頁 |
| 文件大?。?/td> | 302K |
| 代理商： | 68HC05BD7 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁當前第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁
SECTION 10: SYNC PROCESSOR
MOTOROLA
Page 51
MC68HC05BD7 Rev. 2.0
GENERAL RELEASE SPECIFICATION
PRELMNARY
COMP
separator circuit which extracts the VSYNC pulse from
composite input in HSYNC pin. The extracted VSYNC pulse
will be fed into the vertical counter, vertical polarity detection
circuit, and VSYNO output circuit as well. Its measurable
timing is the same as the separate VSYNC pin input. Reset
clears this bit.
VINVO
bit 3
This bit controls the output polarity of the VSYNO signal.
When it is zero, the VSYNO output is identical to the VSYNC
input. When it is one, the inverted VSYNC signal is output to
VSYNO pin.
10.3
Registers
There are five registers associated with the SYNC PROCESSOR module as described
below.
10.3.1
Sync Processor Control and Status Register (SPCSR)
NOTE:
Please don’t use BSET or BCLR to manipulate this register when VSIE is
set and I-bit is clear, or it will cuase abnormal reset.
VSIE
bit 7
When VSync Interrupt Enable (VSIE) bit is set, the VSIF flag
is enabled to generate an interrupt request to the CPU. When
VSIE is cleared, the VSIF flag is prevented from generating an
interrupt request. Reset clears this bit.
The VEDGE bit specifies the triggering edge of VSYNC
interrupt. When it is zero, the rising edge of internal VSYNC
signal which is either from the VSYNC pin or extracted from
the composite input signal will set VSIF flag. When it is one,
the falling edge of internal VSYNC signal will set VSIF flag.
Reset clears this bit.
This flag is a read-only bit and is set by the specified edge of
internal VSYNC signal which is either from the VSYNC pin or
extracted from the composite input signal. The triggering
edge is specified by the VEDGE bit, see the above description
of VEDGE for details. It is cleared by writing a zero to it or
reset.
VEDGE
VSIF
bit 5
0
7
0
0
0
0
0
0
0
6
5
4
3
2
1
0
W
SPCSR
$000C
reset
VSIF
COMP
VEDGE
VSIE
VPOL
HPOL
HINVO
VINVO
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 68HC705BD7 | 8-Bit Microcontroller Units (MCU).(8位微控制器) |
| 68HC05J5A | 8-Bit Microcontroller Units (MCU).(8位微控制器) |
| 68HC705J5A | 8-Bit Microcontroller Units (MCU).(8位微控制器) |
| 68HRC05J5A | 8-Bit Microcontroller Units (MCU).(8位微控制器) |
| 68HRC705J5A | 8-Bit Microcontroller Units (MCU).(8位微控制器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 68HC05C0FN | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microcontroller |
| 68HC05C0P | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microcontroller |
| 68HC05C4AFB | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microcontroller |
| 68HC05C4AFN | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microcontroller |
| 68HC05C4AP | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microcontroller |
發(fā)布緊急采購，3分鐘左右您將得到回復。