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參數(shù)資料
| 型號： | 68HC05BD7 |
| 廠商： | Motorola, Inc. |
| 英文描述： | 8-Bit Microcontroller Units (MCU).(8位微控制器) |
| 中文描述： | 8位微控制器單元（MCU）。（8位微控制器） |
| 文件頁數(shù)： | 28/85頁 |
| 文件大小： | 302K |
| 代理商： | 68HC05BD7 |
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MOTOROLA
Page 18
SECTION 3: CPU CORE
GENERAL RELEASE SPECIFICATION
MC68HC05BD7 Rev. 2.0
location every time an instruction or operand is fetched. Jump, branch, and interrupt
operations load the program counter with an address other than that of the next sequential
location.
3.1.2
Index Register (X)
The index register shown in
Figure 3-1
is an 8-bit register that can perform two functions:
Indexed addressing
Temporary storage
In indexed addressing with no offset, the index register contains the low byte of the operand
address, and the high byte is assumed to be $00. In indexed addressing with an 8-bit offset,
the CPU finds the operand address by adding the index register content to an 8-bit
immediate value. In indexed addressing with a 16-bit offset, the CPU finds the operand
address by adding the index register content to a 16-bit immediate value.
The index register can also serve as an auxiliary accumulator for temporary storage. The
index register is not affected by a reset of the device.
3.1.3
Stack Pointer (SP)
The stack pointer shown in
Figure 3-1
is a 16-bit register. In MCU devices with memory
space less than 64K bytes the unimplemented upper address lines are ignored. The stack
pointer contains the address of the next free location on the stack. During a reset or the
reset stack pointer (RSP) instruction, the stack pointer is set to $00FF. The stack pointer is
then decremented as data is pushed onto the stack and incremented as data is pulled off
the stack.
When accessing memory, the ten most significant bits are permanently set to 0000000011.
The six least significant register bits are appended to these ten fixed bits to produce an
address within the range of $00FF to $00C0. Subroutines and interrupts may use up to 64
($40) locations. If 64 locations are exceeded, the stack pointer wraps around and
overwrites the previously stored information. A subroutine call occupies two locations on
the stack and an interrupt uses five locations.
3.1.4
Program Counter (PC)
The program counter shown in
Figure 3-1
is a 16-bit register. In MCU devices with memory
space less than 64K bytes the unimplemented upper address lines are ignored. The
program counter contains the address of the next instruction or operand to be fetched.
Normally, the address in the program counter increments to the next sequential memory
3.1.5
Condition Code Register (CCR)
The CCR shown in
Figure 3-1
is a 5-bit register in which four bits are used to indicate the
results of the instruction just executed. The fifth bit is the interrupt mask. These bits can be
individually tested by a program, and specific actions can be taken as a result of their
states. The condition code register should be thought of as having three additional upper
bits that are always ones. Only the interrupt mask is affected by a reset of the device. The
following paragraphs explain the functions of the lower five bits of the condition code
register.
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