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參數(shù)資料
| 型號： | 68HC05BD7 |
| 廠商： | Motorola, Inc. |
| 英文描述： | 8-Bit Microcontroller Units (MCU).(8位微控制器) |
| 中文描述： | 8位微控制器單元（MCU）。（8位微控制器） |
| 文件頁數(shù)： | 53/85頁 |
| 文件大?。?/td> | 302K |
| 代理商： | 68HC05BD7 |
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SECTION 9: DDC12AB INTERFACE
MOTOROLA
Page 43
MC68HC05BD7 Rev. 2.0
GENERAL RELEASE SPECIFICATION
PRELMNARY
Bit 3
If the received acknowledge bit (RXAK) is low, it indicates an
acknowledge signal has been received after the completion of
8 data bits transmission on the bus. If RXAK is high, it
indicates no acknowledge signal has been detected at the 9th
clock. Then the module will release the SDA line for the
master to generate ’stop’ or ’repeated start’ condition. It is set
upon reset.
Bit 2
This SCLIF flag is set by the falling edge of SCL line only
when DDC1EN is enabled. This bit is cleared by writing zero
to it, clearing DDC1EN bit or when the DEN is disable.
9.3.4
DDC Status Register (DSR)
This status register is readable only. All bits are cleared upon reset except bit 3 (RXAK) and
bit 1 (TXBE).
RXIF
Bit 7
is loaded with a newly received data. Once the DDRR is
loaded with received data, no more received data can be
loaded to the DDRR register. The only way to release the
DDRR register for loading next received data is that software
reads the data from the DDRR register to clear RXBF flag.
This bit is cleared by writing ’0’ to it or when the DEN is
disabled.
The data Transmit Interrupt Flag is set before the data of the
DDTR register is downloaded to the shift register. It is
software’s responsibility to fill the DDTR register with new
data when this bit is set. This bit is cleared by writing ’0’ to it
or when the DEN is disabled.
The MATCH flag is set when the received data in the DDRR
register is an calling address which matches with the address
or its extended addresses (EXTAD=1) specified in the DADR
register.
The Slave RW bit will indicate the data direction of DDC
protocol. It is updated after the calling address is received in
the DDC2 protocol. When it is one, the master will read the
data from DDC module, so the module is in transmit mode.
When it is zero, the master will send data to the DDC module,
the module is in receive mode. When DDC1EN is set, the
TXIF
Bit 6
MATCH
Bit 5
SRW
Bit 4
RXAK
SCLIF
0
7
TXBE
0
0
0
1
0
1
0
6
5
4
3
2
1
0
RXBF
W
R
DSR
$0019
reset
SCLIF
MATCH
RXAK
SRW
TXIF
RXIF
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