參數(shù)資料
型號(hào)： 62371AB
廠商： Intel Corp.
英文描述： multi-function PCI device(多功能PCI設(shè)備)
中文描述： 多功能PCI設(shè)備（多功能的PCI設(shè)備）
文件頁(yè)數(shù)： 188/284頁(yè)
文件大小： 1042K
代理商： 62371AB
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82371AB (PIIX4)
E
188
4/9/97 2:23 PM PIIX4aDS
INTEL CONFIDENTIAL
(until publication date)
PRELIMINARY
8.9.2.
RTC UPDATE CYCLE
An update cycle occurs once a second, if the SET bit of register B is not set to 1 and the divide chain is properly
configured. During this procedure, the stored time and date are incremented, overflow checked, a matching
alarm condition is checked, and the time and date are rewritten to the RAM locations. The update cycle will start
at least 244
μ
s after the UIP bit of register A is set to 1, and the entire cycle does not take more than 1984
μ
s to
complete. The time and date RAM locations (0–9) are disconnected from the external bus during this time. To
avoid update and data conditions, external RAM access to these locations can safely occur at two times. When
an updated-ended interrupt is detected (almost 999 ms is available to read and write valid time and date data). If
the UIP bit of register A is detected to be low, there is at least 244
μ
s before the update cycle begins. Because
the overflow conditions for leap years and daylight savings adjustments are based on more than one date or time
item, the time before one of these conditions should be set (when adjusting) at least 2 seconds before one of
these conditions to ensure proper operation.
8.9.3.
RTC INTERRUPTS
The real-time clock interrupt is connected to ISA IRQ8#, and is internally routed within PIIX4. If the RTC module
is not enabled, the GPI6 signal is available as the IRQ8# input.
8.9.4.
LOCKABLE RAM RANGES
The real-time clock battery-backed RAM supports two 8-byte ranges that can be enabled via the configuration
space. If the configuration bits are set, the corresponding range in the RAM will not be readable or writeable. A
write cycle to these locations have no effect. A read cycle to these locations do not return the actual location
value. Once enabled, this function can only be disabled by a hard reset.
8.9.5.
RTC EXTERNAL CONNECTIONS
RTC Crystal
The RTC modules requires an externally connected crystal on the RX1 and RX2 pins.
RTC Battery
The RTC modules requires an external battery connection to maintain the RTC block while PIIX4 is not powered
by the system.
Battery characteristics:
Minimum Voltage:
Recommended Batteries: Duracell 2032, 2025, or 2016
2.0V
The battery must also be connected to PIIX4 via isolation diodes. This is both a chip-design requirement, as well
as a UL requirement. The diode circuit allows the RTC-well to be powered by the battery when system power is
not available, but by the system power when it is available. This is done by setting the diode to be reverse
biased when system power is not available.
8.10.
X-Bus Support
PIIX4 provides positive decode (chip selects) and X-Bus buffer control (XDIR# and XOE#) for a real time clock,
keyboard, BIOS, and two programmable IO ranges for PCI and ISA initiated cycles. PIIX4 also generates
RTCALE (address latch enable) for the RTC. The chip selects are generated combinatorially from the ISA
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