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參數(shù)資料
| 型號(hào)： | 62371AB |
| 廠商： | Intel Corp. |
| 英文描述： | multi-function PCI device(多功能PCI設(shè)備) |
| 中文描述： | 多功能PCI設(shè)備（多功能的PCI設(shè)備） |
| 文件頁數(shù)： | 159/284頁 |
| 文件大?。?/td> | 1042K |
| 代理商： | 62371AB |
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Each DMA channel is hardwired to the compatible settings for DMA device size: channels [3:0] are hardwired to
8-bit, count-by-bytes transfers, and channels [7:5] are hardwired to 16-bit, count-by-words (address shifted)
transfers. PIIX4 provides the timing control and data size translation necessary for the DMA transfer between the
memory (ISA or DRAM) and the ISA Bus IO. ISA-Compatible and Type F-DMA timing is supported.
82371AB (PIIX4)
159
4/9/97 2:23 PM PIIX4aDS
INTEL CONFIDENTIAL
(until publication date)
PRELIMINARY
PIIX4 provides 24-bit addressing in compliance with the ISA-Compatible specification. Each channel includes a
16-bit ISA-Compatible Current Register which holds the 16 least-significant bits of the 24-bit address, an ISA-
Compatible Page Register which contains the eight next most significant bits of address.
The DMA controller also features refresh address generation, and autoinitialization following a DMA termination.
The DMA controller is at any time either in master mode or slave mode. In master mode, the DMA controller is
either servicing a DMA slave’s request for DMA cycles, or allowing a 16-bit ISA master to use the bus via a
cascaded DREQ signal. In slave mode, PIIX4 monitors both the ISA Bus and PCI, decoding and responding to
I/O read and write commands that address its registers.
Note that a DMA device (I/O device) is always on the ISA Bus, but the memory referenced is located on either
an ISA Bus device or on PCI. When PIIX4 is running a compatible DMA cycle, it drives the MEMR# or MEMW#
strobes if the address is less than 16 Mbytes (000000h–FFFFFFh). These memory strobes are generated
regardless of whether the cycle is decoded for PCI or ISA memory. The SMEMR# and SMEMW# are generated
if the address is less than 1 Mbytes (0000000h–00FFFFFh). If the address is greater than
16 Mbytes (1000000h–7FFFFFFh), the MEMR# or MEMW# strobe are not generated to avoid aliasing issues.
NOTE
BIOS Programming:
For type F timing mode DMA transfers, the channel must be programmed with a
memory range that will be forwarded to PCI. This means that if BIOS detects that ISA memory is used in
the system (i.e., that the top of memory reported to the OS is higher than the top of memory programmed
in PIIX4 Top of Memory register), the BIOS should not enable type F for any channel.
PIIX4 drives the AEN signal asserted (high) during DMA cycles to prevent the I/O devices from misinterpreting
the DMA cycle as a valid I/O cycle. The BALE signal is also driven high during DMA cycles.
8.4.1.
DMA TRANSFER MODES
The channels can be programmed for any of four transfer modes. The transfer modes include single, block,
demand, or cascade. Each of the three active transfer modes (single, block, and demand), can perform three
different types of transfers (read, write, or verify). Note that memory-to-memory transfers are not supported by
PIIX4.
Single Transfer Mode
In single transfer mode, the DMA is programmed to make one transfer only. The byte/word count is decremented
and the address decremented or incremented following each transfer. When the byte/word count “rolls over”
from zero to FFFFh, a Terminal Count (TC) causes an autoinitialize if the channel has been programmed to do
so.
To be recognized DREQ must be held active until DACK# becomes active. If DREQ is held active throughout
the single transfer, the bus is released after a single transfer. With DREQ asserted high, the DMA I/O device re-
arbitrate for the bus. Upon winning the bus, another single transfer is performed. This allows other ISA bus
masters a chance to acquire the bus.
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