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參數(shù)資料
| 型號： | 5P49EE802NDGI |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 23/26頁 |
| 文件大小： | 0K |
| 描述： | IC CLOCK GENERATOR 28QFN |
| 標準包裝： | 75 |
| 系列： | VersaClock™ |
| 類型： | 時鐘發(fā)生器 |
| PLL： | 帶旁路 |
| 輸入： | LVTTL，晶體 |
| 輸出： | LVCMOS，LVTTL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:7 |
| 差分 - 輸入:輸出： | 無/是 |
| 頻率 - 最大： | 120MHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 1.71 V ~ 1.89 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-VFQFN 裸露焊盤 |
| 供應商設備封裝： | 28-VFQFPN（4x4） |
| 包裝： | 管件 |
| 其它名稱： | 800-2523 |
IDT5P49EE802
VERSACLOCK LOW POWER CLOCK GENERATOR
EEPROM CLOCK GENERATOR
IDT VERSACLOCK LOW POWER CLOCK GENERATOR
6
IDT5P49EE802
REV M 072512
PLL Features and Descriptions
PLL Block Diagram
Crystal Input (XIN/REF)
The crystal oscillators should be fundamental mode quartz
crystals; overtone crystals are not suitable. Crystal
frequency should be specified for parallel resonance with
50
Ω maximum equivalent series resonance. 0
ONXTALB=0 bit needs to be set for XIN/REF.
Crystal Load Capacitors
The device crystal connections should include pads for
small capacitors from X1 to ground and from X2 to ground.
These capacitors are used to adjust the stray capacitance of
the board to match the nominally required crystal load
capacitance. Because load capacitance can only be
increased in this trimming process, it is important to keep
stray capacitance to a minimum by using very short PCB
traces (and no vias) between the crystal and device. Crystal
capacitors must be connected from each of the pins X1 and
X2 to ground.
The crystal cpacitors are internal to the device and have an
effective value of 4pF.
Reference Pre-Divider, Reference Divider,
Feedback-Divider and Post-Divider
Each PLL incorporates an 8-bit reference-scaler and a
11-bit feedback divider which allows the user to generate
four unique non-integer-related frequencies. PLLA and
PLLD each have a feedback pre-divider that provides
additional multiplication for kHz reference clock
applications. Each output divider supports 8-bit post-divider.
The following equation governs how the output frequency is
calculated.
Where FIN is the reference frequency, XDIV is the feedback
pre-divider value, M is the feedback-divider value, D is the
reference divider value, ODIV is the total post-divider value,
and FOUT is the resulting output frequency. Programming
any of the dividers may cause glitches on the outputs.
Ref-Divider
(D) Values
Feedback
Pre-Divider
(XDIV)
Values
Feedback
(M) Values
Programmable
Loop Bandwidth
Spread Spectrum
Generation Capability
PLLA
1 - 255
1 or 4
6 - 2047
Yes
No
PLLB
1 - 255
4
6 - 2047
Yes
PLLC
1 - 255
1 or 8 bit divide
6 - 2047
Yes
No
PLLD
1 - 255
1 or 4
6 - 2047
Yes
No
VCO
D
XDIV
M
(
)
F
OUT =
XDIV*M
D
F
IN *
ODIV
(Eq. 2)
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| 5P49EE802NDGI8 | 制造商:Integrated Device Technology Inc 功能描述:Programmable PLL Clock Generator Quad 28-Pin VFQFPN T/R 制造商:Integrated Device Technology Inc 功能描述:28 QFN (4X4MM) - Tape and Reel 制造商:Integrated Device Technology Inc 功能描述:VERSACLOCK LOW POWER PLL |
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| 5P49EE805NDGI8 | 制造商:Integrated Device Technology Inc 功能描述:Programmable PLL Clock Generator Quad 28-Pin VFQFPN T/R 制造商:Integrated Device Technology Inc 功能描述:28 QFN (GREEN) - Tape and Reel 制造商:Integrated Device Technology Inc 功能描述:PROGRAMMABLE PLL LOW POWER |
| 5P49V5901B000NLGI8 | 功能描述:IC CLOCK GENERATOR 24VFQFPN 制造商:idt, integrated device technology inc 系列:VersaClock? 5 包裝:剪切帶（CT） 零件狀態(tài):有效 類型:* PLL:是 輸入:HCSL，LVCMOS，LVDS，LVPECL，晶體 輸出:HCSL，LVCMOS，LVDS，LVPECL 電路數(shù):1 比率 - 輸入:輸出:2：4 差分 - 輸入:輸出:是/是 頻率 - 最大值:350MHz 分頻器/倍頻器:是/無 電壓 - 電源:1.71 V ~ 3.465 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:24-VFQFN 裸露焊盤 供應商器件封裝:24-VFQFPN（4x4） 標準包裝:1 |
| 5P49V5901B010NLGI8 | 功能描述:IC CLOCK GENERATOR 24VFQFPN 制造商:idt, integrated device technology inc 系列:* 零件狀態(tài):有效 標準包裝:1 |
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