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參數(shù)資料
| 型號： | 5P49EE802NDGI |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 21/26頁 |
| 文件大小： | 0K |
| 描述： | IC CLOCK GENERATOR 28QFN |
| 標(biāo)準(zhǔn)包裝： | 75 |
| 系列： | VersaClock™ |
| 類型： | 時鐘發(fā)生器 |
| PLL： | 帶旁路 |
| 輸入： | LVTTL，晶體 |
| 輸出： | LVCMOS，LVTTL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:7 |
| 差分 - 輸入:輸出： | 無/是 |
| 頻率 - 最大： | 120MHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 1.71 V ~ 1.89 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-VFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 28-VFQFPN（4x4） |
| 包裝： | 管件 |
| 其它名稱： | 800-2523 |
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IDT5P49EE802
VERSACLOCK LOW POWER CLOCK GENERATOR
EEPROM CLOCK GENERATOR
IDT VERSACLOCK LOW POWER CLOCK GENERATOR
4
IDT5P49EE802
REV M 072512
Note *: SEL pins should be controlled by 1.8V LVTTL logic; 3.3V tolerant.
Note 1: Outputs are user programmable to drive single-ended 1.8V/2.5V/3.3V LVTTL as indicated above.
Note 2: Default configuration CLK3=Buffered Reference output. All other outputs are off.
Note 3: Do not power up with SEL[1:0] = 00 (in Power down/Sleep mode).
OUT2
13
O
Adjustable
Configurable clock output 2. Single-ended output voltage levels
are register controlled by either VDDO1, VDDO2 or VDDO3.
SEL1*
14
I
LVTTL
Configuration select pin. Weak internal pull down resistor.
OUT1
15
O
Adjustable
Configurable clock output 1. Single-ended output voltage levels
are register controlled by either VDDO1, VDDO2 or VDDO3.
VDD
16
Power
Device power supply. Connect to 1.8V.
VDD
17
Power
Device power supply. Connect to 1.8V.
OUT0
18
O
Adjustable
Configurable clock output 0. Single-ended output voltage levels
are register controlled by either VDDO1, VDDO2 or VDDO3.
VDDO3
19
Power
Device power supply. Connect to 1.8 to 3.3V. Using register
settings, select output voltage levels for OUT0-OUT5.
SCLK
20
I
LVTTL
I2C clock. Logic levels set by VDDO1. 5V tolerant.
OUT6B
21
O
Adjustable
Configurable clock output 6B. Output voltage levels are
controlled by VDDO1.
OUT6A
22
O
Adjustable
Configurable clock output 6A. Output voltage levels are
controlled by VDDO1.
SDA
23
I/O
LVTTL
Bidirectional I2C data. Logic levels set by VDDO1. 5V tolerant.
VDD
24
Power
Device power supply. Connect to 1.8V.
VDD
25
Power
Device power supply. Connect to 1.8V.
GND
26
Power
Connect to Ground.
XIN/ REF
27
I
LVTTL
MHz CRYSTAL_IN -- Reference crystal input or external
reference clock input. Maximum clock input voltage is 1.8V.
XOUT
28
O
LVTTL
MHz CRYSTAL_OUT -- Reference crystal feedback. Float pin if
using reference input clock.
Pin Name
Pin #
I/O
Pin Type
Pin Description
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 5P49EE802NDGI8 | 制造商:Integrated Device Technology Inc 功能描述:Programmable PLL Clock Generator Quad 28-Pin VFQFPN T/R 制造商:Integrated Device Technology Inc 功能描述:28 QFN (4X4MM) - Tape and Reel 制造商:Integrated Device Technology Inc 功能描述:VERSACLOCK LOW POWER PLL |
| 5P49EE805NDGI | 制造商:Integrated Device Technology Inc 功能描述:Programmable PLL Clock Generator Quad 28-Pin VFQFPN Tube 制造商:Integrated Device Technology Inc 功能描述:28 QFN (GREEN) - Bulk 制造商:Integrated Device Technology Inc 功能描述:PROGRAMMABLE PLL LOW POWER |
| 5P49EE805NDGI8 | 制造商:Integrated Device Technology Inc 功能描述:Programmable PLL Clock Generator Quad 28-Pin VFQFPN T/R 制造商:Integrated Device Technology Inc 功能描述:28 QFN (GREEN) - Tape and Reel 制造商:Integrated Device Technology Inc 功能描述:PROGRAMMABLE PLL LOW POWER |
| 5P49V5901B000NLGI8 | 功能描述:IC CLOCK GENERATOR 24VFQFPN 制造商:idt, integrated device technology inc 系列:VersaClock? 5 包裝:剪切帶（CT） 零件狀態(tài):有效 類型:* PLL:是 輸入:HCSL，LVCMOS，LVDS，LVPECL，晶體 輸出:HCSL，LVCMOS，LVDS，LVPECL 電路數(shù):1 比率 - 輸入:輸出:2：4 差分 - 輸入:輸出:是/是 頻率 - 最大值:350MHz 分頻器/倍頻器:是/無 電壓 - 電源:1.71 V ~ 3.465 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:24-VFQFN 裸露焊盤 供應(yīng)商器件封裝:24-VFQFPN（4x4） 標(biāo)準(zhǔn)包裝:1 |
| 5P49V5901B010NLGI8 | 功能描述:IC CLOCK GENERATOR 24VFQFPN 制造商:idt, integrated device technology inc 系列:* 零件狀態(tài):有效 標(biāo)準(zhǔn)包裝:1 |
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