參數(shù)資料
型號： 54F74DC
英文描述： FLIP-FLOP|DUAL|D TYPE|F-TTL|DIP|14PIN|CERAMIC
中文描述： 觸發(fā)器|雙| D型|架F - TTL電|雙酯| 14PIN |陶瓷
文件頁數(shù)： 5/6頁
文件大?。?/td> 16K
代理商： 54F74DC
CN54F74-X REV 0A0
MICROCIRCUIT DATA SHEET
Electrical Characteristics
AC PARAMETER
(The following conditions apply to all the following parameters, unless otherwise specified.)
AC:
CL=50pf, RL=500 OHMS, TR=2.5ns, TF=2.5ns SEE AC FIGS. Temp Range: 0C to +70C
SYMBOL
PARAMETER
CONDITIONS
NOTES
PIN-
NAME
MIN
MAX
UNIT
SUB-
GROUPS
fMAX
Maximum Clock
Frequency
VCC=+5.0V @ +25C,
VCC=4.5V & 5.5V @ 0/+70C
4
100
MHz
9, 10,
11
tpLH(1)
Propagation Delay
VCC=+5.0V @ +25C,
VCC=4.5V & 5.5V @ 0/+70C
2, 3 CPn/Qn
or Qn
3.8
6.8
ns
9
2, 3 CPn/Qn
or Qn
3.8
7.8
ns
10, 11
tpHL(1)
Propagation Delay
VCC=+5.0V @ +25C,
VCC=4.5V & 5.5V @ 0/+70C
2, 3 CPn/Qn
or Qn
4.4
8.0
ns
9
2, 3 CPn/Qn
or Qn
4.4
9.2
ns
10, 11
tpLH(2)
Propagation Delay
CDn or SDn/Qn or
Qn
VCC=+5.0V @+25C,
VCC=4.5V & 5.5V @ 0/+70C
2, 3
3.2
6.1
ns
9
tpLH(2)
Propagation Delay
CDn or SDn/Qn or
Qn
VCC=+5.0V @+25C,
VCC=4.5V & 5.5V @ 0/+70C
2, 3
3.2
7.1
ns
10, 11
tpHL(2)
Propagation Delay
CDn or SDn/Qn or
Qn
VCC=+5.0V @ +25C,
VCC=4.5V & 5.5V @ 0/+70C
2, 3
3.5
9.0
ns
9
tpHL(2)
Propagation Delay
CDn or SDn/Qn or
Qn
VCC=+5.0V @ +25C,
VCC=4.5V & 5.5V @ 0/+70C
2, 3
3.5
10.5
ns
10, 11
ts(H)
Setup Time HIGH
VCC=+5.0V @ +25C,
VCC=4.5V & 5.5V @ 0/+70C
4
Dn to
CPn
2.0
ns
9, 10,
11
ts(L)
Setup Time LOW
VCC=+5.0V @ +25C,
VCC=4.5V & 5.5V @ 0/+70C
4
Dn to
CPn
3.0
ns
9, 10,
11
th(H/L)
Hold Time HIGH or
LOW
VCC=+5.0V @ +25C,
VCC=4.5V & 5.5V @ 0/+70C
4
Dn to
CPn
1.0
ns
9, 10,
11
tw(H)
Pulse Width HIGH
VCC=+5.0V @ +25C,
VCC=4.5V & 5.5V @ 0/+70C
4
CPn
4.0
ns
9, 10,
11
tw(L)
Pulse Width LOW
VCC=+5.0V @ +25C,
VCC=4.5V & 5.5V @ 0/+70C
4
CPn
5.0
ns
9, 10,
11
tw (L)
Pulse Width LOW
VCC=+5.0V @ +25C,
VCC=4.5V & 5.5V @ 0/+70C
4
CDn or
SDn
4.0
ns
9, 10,
11
tREC
Recovery Time
VCC=+5.0V @ +25C,
VCC=4.5V & 5.5V @ 0/+70C
4
CDn/SDn
to CP
2.0
ns
9, 10,
11
Note 1:
Note 2:
Note 3:
Guaranteed by applying specific input condition and testing VOL & VOH.
Screen tested 100% on each device at +75C temperature only, subgroups A2 & A10.
Sample tested (Method 5005, Table 1) on each MFG. lot at +75C temperature only,
subgroups A2 & A10.
Guaranteed but not tested.
Note 4:
5
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