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參數(shù)資料
| 型號： | 440SPE |
| 廠商： | Applied Micro Circuits Corp. |
| 英文描述： | PowerPC 440SPe Embedded Processor |
| 中文描述： | 嵌入式處理器的PowerPC 440SPe |
| 文件頁數(shù)： | 75/80頁 |
| 文件大?。?/td> | 572K |
| 代理商： | 440SPE |
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PowerPC 440SPe Embedded Processor
Revision 1.23 - Sept 21, 2006
AMCC Proprietary
77
Preliminary Data Sheet
Initialization
The PPC440SPe provides the option for setting initial parameters based on default values or by reading them from
a serial “bootstrap” ROM attached to the IIC0 bus. These options are defined by strapping on three external pins
(see “Strapping” below).
Strapping
While the SysReset input pin is low (system reset), the state of certain I/O pins is read to enable certain default
initial conditions prior to PPC440SPe start-up. The actual capture instant is the nearest SysClk edge before the
deassertion of reset. These pins must be strapped using external pull-up (logical 1) or pull-down (logical 0)
resistors to select the desired default conditions. They are used for strap functions only during reset. Following
reset they are used for normal functions.
The following table lists the strapping pins along with their functions and strapping options:
Serial Bootstrap ROM
During reset, if the serial device is enabled, initial conditions can be read from a ROM connected to the IIC0 port. In
this case, at the de-assertion of SysReset, the PPC440SPe sequentially reads up to 32 bytes from the ROM device
on the IIC0 port and sets the SDR0_SDSTP0 - SDR0_SDSTP7 registers accordingly.
The initialization settings and their default values are covered in detail in the PPC440SPe Embedded Processor
User’s Manual.
Table 21. Strapping Pin Assignments
Function
Option
Pin Strapping
Bit 0
H13
(UART0_DCD)
Bit 1
C12
(UART0_DSR)
Bit2
B08
(UART0_CTS)
Serial Bootstrap ROM is disabled (Bit 0 off).
Refer to the IIC Bootstrap Controller chapter in the
PPC440SPe Embedded Processor User’s Manual
for details.
Boot from EBC
0
Boot from PCI
0
1
Serial Bootstrap ROM is enabled (Bit 0 on).
The options being selected are the IIC0 slave
address that responds with strapping data and
reading 128 bits from the Bootstrap ROM.
0x54
1
0
0x50
1
0
Serial Bootstrap ROM is enabled (Bit 0 on).
The options being selected are the IIC0 slave
address that responds with strapping data and
reading 256 bits from the Bootstrap ROM.
0x54
1
0
1
0x50
1
相關PDF資料 |
PDF描述 |
|---|---|
| 440SP | PowerPC 440SP Embedded Processor |
| 4414-308 | 8 POS SOIC ADAPTER |
| 4414-308LF | 8 POS SOIC ADAPTER |
| 4414-314 | 14 POS SOIC ADAPTER |
| 4414-314LF | 14 POS SOIC ADAPTER |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| 440SRIB | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SMOKE ALARM 12-28VDC B/BK |
| 440SS001M08 | 制造商:GLENAIR 制造商全稱:Glenair, Inc. 功能描述:EMI/RFI Crimp Ring Adapter Direct Coupling - Standard Profile |
| 440SS001M09 | 制造商:GLENAIR 制造商全稱:Glenair, Inc. 功能描述:EMI/RFI Crimp Ring Adapter Direct Coupling - Standard Profile |
| 440SS001M10 | 制造商:GLENAIR 制造商全稱:Glenair, Inc. 功能描述:EMI/RFI Crimp Ring Adapter Direct Coupling - Standard Profile |
| 440SS001M11 | 制造商:GLENAIR 制造商全稱:Glenair, Inc. 功能描述:EMI/RFI Crimp Ring Adapter Direct Coupling - Standard Profile |
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