參數(shù)資料
型號(hào)： 440SPE
廠商： Applied Micro Circuits Corp.
英文描述： PowerPC 440SPe Embedded Processor
中文描述： 嵌入式處理器的PowerPC 440SPe
文件頁(yè)數(shù)： 60/80頁(yè)
文件大?。?/td> 572K
代理商： 440SPE
PowerPC 440SPe Embedded Processor
Revision 1.23 - Sept 21, 2006
AMCC Proprietary
63
Preliminary Data Sheet
Figure 4. Clock Timing Waveform
Spread Spectrum Clocking
Care must be taken when using a spread spectrum clock generator (SSCG) with the PPC440SPe. This controller
uses a PLL for clock generation inside the chip. The accuracy with which the PLL follows the SSCG is referred to
as tracking skew. The PLL bandwidth and phase angle determine how much tracking skew there is between the
SSCG and the PLL for a given frequency deviation and modulation frequency. When using an SSCG with the
PPC440SPe the following conditions must be met:
The frequency deviation must not violate the minimum clock cycle time. Therefore, when operating the
PPC440SPe with one or more internal clocks at their maximum supported frequency, the SSCG can only lower
the frequency.
The maximum frequency deviation cannot exceed -1%, and the modulation frequency cannot exceed 40kHz.
In some cases, on-board PPC440SPe peripherals impose more stringent requirements.
Use the Peripheral Bus Clock for logic that is synchronous to the peripheral bus since this clock tracks the
modulation.
Use the DDR SDRAM MemClkOut since it also tracks the modulation.
Processor Clock (CPU Clock)
FC
Frequency
400
666.66
MHz
TC
Period
1.5
2.5
ns
MemClkOut
FC
Frequency
200
333.33
MHz
TC
Period
3
5
ns
TCH
High time
45% of nominal period
55% of nominal period
ns
OPB Clock and PerClk
FC
Frequency
–
83.33
MHz
TC
Period
12
–
ns
MAL Clock
FC
Frequency
45
83.33
MHz
TC
Period
12
22.2
ns
Table 12. Clocking Specifications
Symbol
Parameter
Min
Max
Units
TCL
TCH
TC
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