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參數(shù)資料
| 型號： | 39VF6401 |
| 廠商： | Silicon Storage Technology, Inc. |
| 元件分類： | FLASH |
| 英文描述： | 64 Mbit (x16) Multi-Purpose Flash Plus |
| 中文描述： | 64兆位（x16）的多功能閃存+ |
| 文件頁數(shù)： | 17/32頁 |
| 文件大小： | 513K |
| 代理商： | 39VF6401 |
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Preliminary Specifications
16 Mbit / 32 Mbit / 64 Mbit Multi-Purpose Flash Plus
SST39VF1601 / SST39VF3201 / SST39VF6401
SST39VF1602 / SST39VF3202 / SST39VF6402
17
2003 Silicon Storage Technology, Inc.
S71223-03-000
11/03
FIGURE 7: T
OGGLE
B
ITS
T
IMING
D
IAGRAM
FIGURE 8: WE# C
ONTROLLED
C
HIP
-E
RASE
T
IMING
D
IAGRAM
1223 F07.3
ADDRESS AMS-0
DQ
6
and DQ
2
WE#
OE#
CE#
TOE
TOEH
TCE
TOES
TWO READ CYCLES
WITH SAME OUTPUTS
Note:
A
MS
= Most significant address
A
MS
= A
19
for SST39VF1601/1602, A
20
for SST39VF3201/3202, and A
21
for SST39VF6401/6402
1223 F08.4
ADDRESS AMS-0
DQ15-0
WE#
SW0
SW1
SW2
SW3
SW4
SW5
5555
2AAA
2AAA
5555
5555
XX55
XX10
XX55
XXAA
XX80
XXAA
5555
OE#
CE#
SIX-BYTE CODE FOR CHIP-ERASE
TSCE
TWP
Note: This device also supports CE# controlled Chip-Erase operation. The WE# and CE# signals are
interchageable as long as minimum timings are met. (See Table 17)
A
MS
= Most significant address
A
MS
= A
19
for SST39VF1601/1602, A
20
for SST39VF3201/3202, and A
21
for SST39VF6401/6402
WP# must be held in proper logic state (V
IH
) 1 μs prior to and 1 μs after the command sequence
X can be V
IL
or V
IH
, but no other value
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