參數(shù)資料
型號： 39VF6401
廠商： Silicon Storage Technology, Inc.
元件分類： FLASH
英文描述： 64 Mbit (x16) Multi-Purpose Flash Plus
中文描述： 64兆位（x16）的多功能閃存+
文件頁數(shù)： 13/32頁
文件大?。?/td> 513K
代理商： 39VF6401
Preliminary Specifications
16 Mbit / 32 Mbit / 64 Mbit Multi-Purpose Flash Plus
SST39VF1601 / SST39VF3201 / SST39VF6401
SST39VF1602 / SST39VF3202 / SST39VF6402
13
2003 Silicon Storage Technology, Inc.
S71223-03-000
11/03
TABLE 12: DC O
PERATING
C
HARACTERISTICS
V
DD
= 2.7-3.6V
1
Symbol
I
DD
Parameter
Power Supply Current
Limits
Max
Test Conditions
Address input=V
ILT
/V
IHT2
, at f=5 MHz,
V
DD
=V
DD
Max
CE#=V
IL
, OE#=WE#=V
IH
, all I/Os open
CE#=WE#=V
IL
, OE#=V
IH
CE#=V
IHC
, V
DD
=V
DD
Max
CE#=V
ILC
, V
DD
=V
DD
Max
All inputs=V
SS
or V
DD,
WE#=V
IHC
V
IN
=GND to V
DD
, V
DD
=V
DD
Max
WP#=GND to V
DD
or RST#=GND to V
DD
Min
Units
Read
3
Program and Erase
Standby V
DD
Current
Auto Low Power
18
35
20
20
mA
mA
μA
μA
I
SB
I
ALP
I
LI
I
LIW
Input Leakage Current
Input Leakage Current
on WP# pin and RST#
Output Leakage Current
Input Low Voltage
Input Low Voltage (CMOS)
Input High Voltage
Input High Voltage (CMOS)
Output Low Voltage
Output High Voltage
1
μA
μA
10
I
LO
V
IL
V
ILC
V
IH
V
IHC
V
OL
V
OH
10
0.8
0.3
μA
V
V
V
V
V
V
V
OUT
=GND to V
DD
, V
DD
=V
DD
Max
V
DD
=V
DD
Min
V
DD
=V
DD
Max
V
DD
=V
DD
Max
V
DD
=V
DD
Max
I
OL
=100 μA, V
DD
=V
DD
Min
I
OH
=-100 μA, V
DD
=V
DD
Min
0.7V
DD
V
DD
-0.3
0.2
V
DD
-0.2
T12.8 1223
1. Typical conditions for the Active Current shown on the front page of the data sheet are average values at 25°C
(room temperature), and V
DD
= 3V. Not 100% tested.
2. See Figure 17
3. The I
DD
current listed is typically less than 2mA/MHz, with OE# at V
IH.
Typical V
DD
is 3V.
TABLE 13: R
ECOMMENDED
S
YSTEM
P
OWER
-
UP
T
IMINGS
Symbol
T
PU-READ1
T
PU-WRITE1
Parameter
Power-up to Read Operation
Power-up to Program/Erase Operation
Minimum
100
100
Units
μs
μs
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
T13.0 1223
TABLE 14: C
APACITANCE
(Ta = 25°C, f=1 Mhz, other pins open)
Parameter
C
I/O1
C
IN1
Description
I/O Pin Capacitance
Input Capacitance
Test Condition
V
I/O
= 0V
V
IN
= 0V
Maximum
12 pF
6 pF
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
T14.0 1223
TABLE 15: R
ELIABILITY
C
HARACTERISTICS
Symbol
N
END1,2
T
DR1
I
LTH1
Parameter
Endurance
Data Retention
Latch Up
Minimum Specification
10,000
100
100 + I
DD
Units
Cycles
Years
mA
Test Method
JEDEC Standard A117
JEDEC Standard A103
JEDEC Standard 78
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
2. N
END
endurance rating is qualified as a 10,000 cycle minimum for the whole device. A sector- or block-level rating would result in a
higher minimum specification.
T15.2 1223
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