參數(shù)資料
型號： 3850
廠商： Mitsubishi Electric Corporation
英文描述： SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
中文描述： 單芯片8位CMOS微機(jī)
文件頁數(shù)： 92/99頁
文件大?。?/td> 1384K
代理商： 3850
92
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3850 Group (Spec. H/A)
Table 37 Switching characteristics (1)
(V
CC
= 4.0 to 5.5 V, V
SS
= 0 V, T
a
= –20 to 85 °C, unless otherwise noted)
Table 38 Switching characteristics (2)
(V
CC
= 2.7 to 5.5 V, V
SS
= 0 V, T
a
= –20 to 85 °C, unless otherwise noted)
Serial I/O1 clock output
“
H
”
pulse width
Serial I/O1 clock output
“
L
”
pulse width
Serial I/O1 output delay time
(Note 1)
Serial I/O1 output valid time
(Note 1)
Serial I/O1 clock output rising time
Serial I/O1 clock output falling time
Serial I/O2 clock output
“
H
”
pulse width
Serial I/O2 clock output
“
L
”
pulse width
Serial I/O2 output delay time
(Note 2)
Serial I/O2 output valid time
(Note 2)
Serial I/O2 clock output falling time
CMOS output rising time
(Note 3)
CMOS output falling time
(Note 3)
t
WH
(S
CLK1
)
t
WL
(S
CLK1
)
t
d
(S
CLK1
-T
X
D)
t
v
(S
CLK1
-T
X
D)
t
r
(S
CLK1
)
t
f
(S
CLK1
)
t
WH
(S
CLK2
)
t
WL
(S
CLK2
)
t
d
(S
CLK2
-S
OUT2
)
t
v
(S
CLK2
-S
OUT2
)
t
f
(S
CLK2
)
t
r
(CMOS)
t
f
(CMOS)
Limits
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Parameter
Min.
t
C
(S
CLK1
)/2
–
30
t
C
(S
CLK1
)/2
–
30
–
30
t
C
(S
CLK2
)/2
–
160
t
C
(S
CLK2
)/2
–
160
0
Typ.
10
10
Max.
140
30
30
200
30
30
30
Symbol
Unit
Notes 1:
When the P2
5
/T
X
D P-channel output disable bit of the UART control register (bit 4 of address 001B
16
) is
“
0
”
.
2:
When the P0
1
/S
OUT2
and P0
2
/S
CLK2
P-channel output disable bit of the Serial I/O2 control register 1 (bit 7 of address 0015
16
) is
“
0
”
.
3:
The X
OUT
pin is excluded.
Test conditions
Fig. 78
Serial I/O1 clock output
“
H
”
pulse width
Serial I/O1 clock output
“
L
”
pulse width
Serial I/O1 output delay time
(Note 1)
Serial I/O1 output valid time
(Note 1)
Serial I/O1 clock output rising time
Serial I/O1 clock output falling time
Serial I/O2 clock output
“
H
”
pulse width
Serial I/O2 clock output
“
L
”
pulse width
Serial I/O2 output delay time
(Note 2)
Serial I/O2 output valid time
(Note 2)
Serial I/O2 clock output falling time
CMOS output rising time
(Note 3)
CMOS output falling time
(Note 3)
t
WH
(S
CLK1
)
t
WL
(S
CLK1
)
t
d
(S
CLK1
-T
X
D)
t
v
(S
CLK1
-T
X
D)
t
r
(S
CLK1
)
t
f
(S
CLK1
)
t
WH
(S
CLK2
)
t
WL
(S
CLK2
)
t
d
(S
CLK2
-S
OUT2
)
t
v
(S
CLK2
-S
OUT2
)
t
f
(S
CLK2
)
t
r
(CMOS)
t
f
(CMOS)
Limits
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Parameter
Min.
t
C
(S
CLK1
)/2
–
50
t
C
(S
CLK1
)/2
–
50
–
30
t
C
(S
CLK2
)/2
–
240
t
C
(S
CLK2
)/2
–
240
0
Typ.
20
20
Max.
350
50
50
400
50
50
50
Symbol
Unit
Notes 1:
When the P2
5
/T
X
D P-channel output disable bit of the UART control register (bit 4 of address 001B
16
) is
“
0
”
.
2:
When the P0
1
/S
OUT2
and P0
2
/S
CLK2
P-channel output disable bit of the Serial I/O2 control register 1 (bit 7 of address 0015
16
) is
“
0
”
.
3:
The X
OUT
pin is excluded.
Test conditions
Fig. 78
Switching characteristics
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