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參數(shù)資料
| 型號： | 3850 |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| 中文描述： | 單芯片8位CMOS微機(jī) |
| 文件頁數(shù)： | 33/99頁 |
| 文件大?。?/td> | 1384K |
| 代理商： | 3850 |
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33
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3850 Group (Spec. H/A)
(2) Asynchronous Serial I/O (UART) Mode
Clock asynchronous serial I/O mode (UART) can be selected by
clearing the serial I/O1 mode selection bit (b6) of the serial I/O1
control register to
“
0
”
.
Eight serial data transfer formats can be selected, and the transfer
formats used by a transmitter and receiver must be identical.
The transmit and receive shift registers each have a buffer, but the
two buffers have the same address in memory. Since the shift reg-
ister cannot be written to or read from directly, transmit data is
written to the transmit buffer register, and receive data is read
from the receive buffer register.
The transmit buffer register can also hold the next data to be
transmitted, and the receive buffer register can hold a character
while the next character is being received.
Fig. 28 Block diagram of UART serial I/O1
X
IN
1/4
OE
r
l
t
s
P
E FE
1
/
1
6
1/16
Data bus
R
l
e
e
c
c
t
i
e
o
i
v
e
b
i
b
t
u
f
f
e
r
r
e
g
i
s
t
e
r
A
d
d
r
e
s
s
0
0
1
8
1
6
R
e
c
e
i
v
e
s
h
i
f
t
r
e
g
i
s
t
e
r
Receive buffer full flag (RBF)
R
c
e
i
v
e
i
n
t
e
r
r
u
e
p
t
r
e
q
u
e
s
t
(
R
I
)
B
a
u
d
Address 001C
16
r
a
t
e
g
e
n
e
r
a
t
o
r
Frequency division ratio 1/(n+1)
ST/SP/PA generator
Transmit buffer register
Data bus
T
r
a
n
s
m
i
t
s
h
i
f
t
r
e
g
i
s
t
e
r
A
d
d
r
e
s
s
0
0
1
8
1
6
Transmit shift completion flag (TSC)
Transmit buffer empty flag (TBE)
A
d
r
e
Serial I/O1 status register
Transmit interrupt request (TI)
d
s
s
0
0
1
9
1
6
S
T
d
e
t
e
c
t
o
r
SP detector
UART control register
A
d
d
r
e
s
s
0
0
1
B
1
6
C
h
a
r
a
c
t
e
r
l
e
n
g
t
h
s
e
l
e
c
t
i
o
n
b
i
t
A
d
d
r
e
s
s
0
0
1
A
1
6
B
R
G
c
o
u
n
t
s
o
u
r
c
e
s
e
l
e
c
t
i
o
n
b
i
t
Transmit interrupt source selection bit
S
e
r
i
a
l
I
/
O
1
s
y
n
c
h
r
o
n
o
u
s
c
l
o
c
k
s
e
l
e
c
t
i
o
n
b
i
t
Clock control circuit
C
h
a
r
a
7
8 bits
c
t
e
i
e
n
g
t
h
s
e
n
b
S
e
r
i
a
l
I
/
O
1
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
P2
6
/S
CLK
P
2
4
/
R
X
D
P
2
5
/
T
X
D
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